_primary.vhd

实现乒乓缓存

library verilog;
use verilog.vl_types.all;
entity front is
    port(
        clk_5m          : in     vl_logic;
        rst             : in     vl_logic;
        nd              : in     vl_logic;
        indata          : in     vl_logic_vector(15 downto 0);
        a               : out    vl_logic_vector(15 downto 0);
        b               : out    vl_logic_vector(15 downto 0);
        rdy_a           : out    vl_logic;
        rdy_b           : out    vl_logic
    );
end front;