dp_ram.v

verilog

module dp_ram(rdata, wdata, waddr, raddr, wclken, wclk);
	parameter DATA_WIDTH = 8; 				
	parameter ADDR_WIDTH = 4; 				
	parameter DEPTH = 1<<ADDR_WIDTH; 	
	
	output [DATA_WIDTH-1:0] rdata;
	input [DATA_WIDTH-1:0] wdata;
	input [ADDR_WIDTH-1:0] waddr, raddr;
	input wclken, wclk;

	reg [DATA_WIDTH-1:0] MEM [0:DEPTH-1];
	always @(posedge wclk)
		if (wclken) MEM[waddr] <= wdata;

	assign rdata = MEM[raddr];		
endmodule