wptr_full.v

verilog

module wptr_full (wfull, wptr, afull_n, wreq, wclk, wrst_n);
	parameter ADDR_WIDTH = 4;
	output wfull;
	output [ADDR_WIDTH-1:0] wptr;
	input afull_n;
	input wreq, wclk, wrst_n;
	reg [ADDR_WIDTH-1:0] wptr, wbin;
	reg wfull, wfull2;
	wire [ADDR_WIDTH-1:0] wgnext, wbnext;
	
	
	always @(posedge wclk or negedge wrst_n)
		if (!wrst_n) begin
			wbin <= 0;
			wptr <= 0;
		end
		else begin
			wbin <= wbnext;
			wptr <= wgnext;
		end

	
	assign wbnext = !wfull ? wbin + wreq : wbin;
	assign wgnext = (wbnext>>1) ^ wbnext; 

	always @(posedge wclk or negedge wrst_n or negedge afull_n)
		if (!wrst_n ) 
			{wfull,wfull2} <= 2'b00;
		else if (!afull_n) 
			{wfull,wfull2} <= 2'b11;
		else 
			{wfull,wfull2} <= {wfull2,~afull_n};
endmodule