mux1-8.vhl

8选1数据选择器行为建模及测试Verilog代码

`timescale 1ps / 1ps

input [0:7] D_In ;
wire [0:7] D_In ;
input Cs ;
wire Cs ;
input [0:2] OP ;
wire [0:2] OP ;

output D_Out ;
reg D_Out ;

always 
 @(D_In or OP or Cs)

 begin 
  if(Cs)
   begin
    case (OP)
     3'b 000: D_Out = D_In[0];  
     3'b 001: D_Out = D_In[1];
     3'b 010: D_Out = D_In[2];
     3'b 011: D_Out = D_In[3];
     3'b 100: D_Out = D_In[4];
     3'b 101: D_Out = D_In[5];
     3'b 110: D_Out = D_In[6];
     3'b 111: D_Out = D_In[7]; 
     default D_Out = 1'b 0;
    endcase 
   end  
  end 


endmodule

 

 

测试：

`timescale 1ps / 1ps
module Mux8x1_tb;


reg [0:7]D_In;
tri D_Out;
reg Cs;
reg [0:2]OP;


 Mux8x1 UUT (
  .D_In(D_In),
  .D_Out(D_Out),
  .Cs(Cs),
  .OP(OP));
 
 initial
 begin:ONLY_ONCE

 reg [3:0] pal;


 D_In = 8'b 11001001; 
  
  for(pal=0; pal<16; pal = pal +1)
   begin
    #10;
    {Cs,OP } = pal;
   end 
  
 end
endmodule