📄 decoder.v
字号:
src_sel3 = `AS3_DC;
comp_sel = `CSS_AZ;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`JZ : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = eq;
pc_sel = `PIS_ALU;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_AZ;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`MOVC_DP :begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `AS3_DP;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_Y;
rom_addr_sel = `RAS_DES;
ext_addr_sel = `EAS_DC;
end
`MOVC_PC :begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `AS3_DP;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_Y;
rom_addr_sel = `RAS_DES;
ext_addr_sel = `EAS_DC;
end
`SJMP : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_Y;
pc_sel = `PIS_ALU;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
default begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
endcase
2'b11:
casex (op)
`CJNE_R : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_IMM;
src_sel2 = `ASS_OP2;
alu_op = `ALU_PCS;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_OP3;
src_sel3 = `AS3_PC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`CJNE_I : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_IMM;
src_sel2 = `ASS_OP2;
alu_op = `ALU_PCS;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_OP3;
src_sel3 = `AS3_PC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`CJNE_D : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_IMM;
src_sel2 = `ASS_OP2;
alu_op = `ALU_PCS;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_OP3;
src_sel3 = `AS3_PC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`CJNE_C : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_IMM;
src_sel2 = `ASS_OP2;
alu_op = `ALU_PCS;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_OP3;
src_sel3 = `AS3_PC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`DJNZ_R : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_IMM;
src_sel2 = `ASS_OP2;
alu_op = `ALU_PCS;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_OP2;
src_sel3 = `AS3_PC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`DJNZ_D : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_IMM;
src_sel2 = `ASS_OP2;
alu_op = `ALU_PCS;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_OP3;
src_sel3 = `AS3_PC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`RET : begin
ram_rd_sel = `RRS_SP;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_RAM;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_Y;
pc_sel = `PIS_SP;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`RETI : begin
ram_rd_sel = `RRS_SP;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_RAM;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_Y;
pc_sel = `PIS_SP;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
default begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
endcase
default: begin
casex (op_in)
`ACALL :begin
ram_rd_sel = 2'bxx;
ram_wr_sel = `RWS_SP;
src_sel1 = `ASS_IMM;
src_sel2 = 2'bxx;
alu_op = `ALU_NOP;
imm_sel = `IDS_PCL;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_Y;
pc_sel = `PIS_I11;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`AJMP : begin
ram_rd_sel = 2'bxx;
ram_wr_sel = 2'bxx;
src_sel1 = 2'bxx;
src_sel2 = 2'bxx;
alu_op = 4'bxxxx;
imm_sel = 2'bxx;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_Y;
pc_sel = `PIS_I11;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`ADD_R : begin
ram_rd_sel = `RRS_RN;
ram_wr_sel = `RWS_ACC;
src_sel1 = `ASS_ACC;
src_sel2 = `ASS_RAM;
alu_op = `ALU_ADD;
wr = 1'b1;
psw_set = `PS_AC;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`ADDC_R : begin
ram_rd_sel = `RRS_RN;
ram_wr_sel = `RWS_ACC;
src_sel1 = `ASS_ACC;
src_sel2 = `ASS_RAM;
alu_op = `ALU_ADD;
wr = 1'b1;
psw_set = `PS_AC;
cy_sel = `CY_PSW;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`ANL_R : begin
ram_rd_sel = `RRS_RN;
ram_wr_sel = `RWS_ACC;
src_sel1 = `ASS_ACC;
src_sel2 = `ASS_RAM;
alu_op = `ALU_AND;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`CJNE_R : begin
ram_rd_sel = `RRS_RN;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_IMM;
src_sel2 = `ASS_RAM;
alu_op = `ALU_SUB;
wr = 1'b0;
psw_set = `PS_CY;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_OP2;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`DEC_R : begin
ram_rd_sel = `RRS_RN;
ram_wr_sel = `RWS_RN;
src_sel1 = `ASS_RAM;
src_sel2 = `ASS_ZERO;
alu_op = `ALU_SUB;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_1;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`DJNZ_R : begin
ram_rd_sel = `RRS_RN;
ram_wr_sel = `RWS_RN;
src_sel1 = `ASS_RAM;
src_sel2 = `ASS_ZERO;
alu_op = `ALU_SUB;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_1;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`INC_R : begin
ram_rd_sel = `RRS_RN;
ram_wr_sel = `RWS_RN;
src_sel1 = `ASS_RAM;
src_sel2 = `ASS_ZERO;
alu_op = `ALU_ADD;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_1;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
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