disasm_raw.v

使用CPLD仿真一个80383的CPU,很值得参考一下,难得

 
 
case (opcode)
32'b00110111????????????????????????: /* AAA 1 */
32'b1101010100001010????????????????: /* AAD 2 */
32'b1101010000001010????????????????: /* AAM 2 */
32'b00111111????????????????????????: /* AAS 1 */
32'b0001000?11??????????????????????: /* ADC 2 reg1 to reg2 */
32'b0001001?11??????????????????????: /* ADC 2 reg2 to reg1 */
32'b0001001?????????????????????????: /* ADC 2 mem to reg */
32'b0001000?????????????????????????: /* ADC 2 reg to mem */
32'b100000??11010???????????????????: /* ADC 3 immediate to reg */
32'b0001010?????????????????????????: /* ADC 2 immediage to AL,AX or EAX */
32'b100000?????010??????????????????: /* ADC 3 immediage to mem */
32'b0000000?11??????????????????????: /* ADD 2 reg1 to reg2 */
32'b0000001?11??????????????????????: /* ADD 2 reg2 to reg1 */
32'b0000001?????????????????????????: /* ADD 2 mem to reg */
32'b0000000?????????????????????????: /* ADD 2 reg to mem */
32'b100000??11000???????????????????: /* ADD 3 immediate to reg */
32'b0000010?????????????????????????: /* ADD 2 imediate to AL,AX,or EAX */
32'b100000?????000??????????????????: /* ADD 3 imediate to mem */
32'b0010000?11??????????????????????: /* AND 2 reg1 to reg2 */
32'b0010001?11??????????????????????: /* AND 2 reg2 to reg1 */
32'b0010001?????????????????????????: /* AND 2 mem to reg */
32'b0010000?????????????????????????: /* AND 2 reg to mem */
32'b100000??11100???????????????????: /* AND 3 immediate to reg */
32'b0010010?????????????????????????: /* AND 2 immediate to AL,AX,EAX */
32'b100000?????100??????????????????: /* AND 3 immediate to mem */
32'b0110001111??????????????????????: /* ARPL 2 from reg */
32'b01100011????????????????????????: /* ARPL 2 from mem */
32'b01100010????????????????????????: /* BOUND 2 */
32'b000011111011110011??????????????: /* BSF 3 reg1,reg2 */
32'b0000111110111100????????????????: /* BSF 3 mem,reg */
32'b000011111011110111??????????????: /* BSR 3 reg1,reg2 */
32'b0000111110111101????????????????: /* BSR 3 mem,reg */
32'b0000111111001???????????????????: /* BSWAP 2 */
32'b000011111011101011100???????????: /* BT 4 reg,immediate */
32'b0000111110111010???100??????????: /* BT 4 mem,immediate */
32'b000011111010001111??????????????: /* BT 3 reg1,reg2 */
32'b0000111110100011????????????????: /* BT 3 mem,reg */
32'b000011111011101011111???????????: /* BTC 4 reg,immediate */
32'b0000111110111010???111??????????: /* BTC 4 mem,immediate */
32'b000011111011101111??????????????: /* BTC 3 reg1,reg2 */
32'b0000111110111011????????????????: /* BTC 3 mem,reg */
32'b000011111011101011110???????????: /* BTR 4 reg,immediate */
32'b0000111110111010???110??????????: /* BTR 4 mem,immediate */
32'b000011111011001111??????????????: /* BTR 3 reg1,reg2 */
32'b0000111110110011????????????????: /* BTR 3 mem,reg */
32'b000011111011101011101???????????: /* BTS 4 reg,immediate */
32'b0000111110111010???101??????????: /* BTS 4 mem,immediate */
32'b000011111010101111??????????????: /* BTS 3 reg1,reg2 */
32'b0000111110101011????????????????: /* BTS 3 mem,reg */
32'b11101000????????????????????????: /* CALL 3 same segment direct */
32'b1111111111010???????????????????: /* CALL 2 same segment reg indirect */
32'b11111111???010??????????????????: /* CALL 2 same segment mem indirect */
32'b10011010????????????????????????: /* CALL 2 other segment direct */
32'b11111111???011??????????????????: /* CALL 2 other segment indirect */
32'b10011000????????????????????????: /* CBW 1 */
32'b10011001????????????????????????: /* CDQ 1 */
32'b11111000????????????????????????: /* CLC 1 */
32'b11111100????????????????????????: /* CLD 1 */
32'b11111010????????????????????????: /* CLI 1 */
32'b0000111100000110????????????????: /* CLTS 2 */
32'b11110101????????????????????????: /* CMC 1 */
32'b0011100?11??????????????????????: /* CMP 2 reg1 reg2 */
32'b0011101?11??????????????????????: /* CMP 2 reg2 reg1 */
32'b0011100?????????????????????????: /* CMP 2 mem reg */
32'b0011101?????????????????????????: /* CMP 2 reg mem */
32'b100000??11111???????????????????: /* CMP 3 immediate reg */
32'b0011110?????????????????????????: /* CMP 2 immediate with AL,AX or EAX */
32'b100000?????111??????????????????: /* CMP 3 immedaite with mem */
32'b1010011?????????????????????????: /* CMPS 1 */
32'b000011111011000?11??????????????: /* CMPXCHG 3 reg1,reg2 */
32'b000011111011000?????????????????: /* CMPXCHG 3 mem,reg */
32'b0000111110100010????????????????: /* CPUID 2 */
32'b10011001????????????????????????: /* CWD 1 */
32'b10011000????????????????????????: /* CWDE 1 */
32'b00100111????????????????????????: /* DAA 1 */
32'b00101111????????????????????????: /* DAS 1 */
32'b1111111?11001???????????????????: /* DEC 2 reg */
32'b01001???????????????????????????: /* DEC 1 reg(altmeate encoding) */
32'b1111111????001??????????????????: /* DEC 2 */
32'b1111011?11110???????????????????: /* DIV 2 AL,AX,EAX by reg */
32'b1111011????110??????????????????: /* DIV 2 AL,AX,EAX by mem */
32'b11001000????????????????????????: /* ENTER 4 */
32'b11110100????????????????????????: /* HLT 1 */
32'b1111011?11111???????????????????: /* IDIV 2 AL,AX,EAX by reg */
32'b1111011????111??????????????????: /* IDIV 2 AL,AX,EAX by mem */
32'b1111011?11101???????????????????: /* IMUL 2 AL,AX,EAX with reg */
32'b1111011????101??????????????????: /* IMUL 2 AL,AX,EAX with mem */
32'b0000111110101111????????????????: /* IMUL 3 reg1 with reg2 */
32'b0000111110101111????????????????: /* IMUL 3 reg with mem */
32'b011010?111??????????????????????: /* IMUL 3 reg1 with immediate to reg2 */
32'b011010?1????????????????????????: /* IMUL 3 mem with immediate to reg */
32'b1110010?????????????????????????: /* IN 2 fixed port */
32'b1110110?????????????????????????: /* IN 2 varable port */
32'b1111111?11000???????????????????: /* INC 2 reg */
32'b01000???????????????????????????: /* INC 1 reg(alternate encoding) */
32'b1111111????000??????????????????: /* INC 2 mem */
32'b0110110?????????????????????????: /* INS 1 */
32'b11001101????????????????????????: /* INT 2 */
32'b11001100????????????????????????: /* INT 1 */
32'b11001110????????????????????????: /* INTO 1 */
32'b0000111100001000????????????????: /* INVD 2 */
32'b0000111100000001???111??????????: /* INVLPG 3 */
32'b11001111????????????????????????: /* IRET 1 */
32'b0111????????????????????????????: /* JCC 1 */
32'b000011111000????????????????????: /* JCC 3 */
32'b11100011????????????????????????: /* JCXZ 2 */
32'b11101011????????????????????????: /* JMP 2 short */
32'b11101001????????????????????????: /* JMP 2 direct */
32'b1111111111100???????????????????: /* JMP 2 reg indirect */
32'b11111111???100??????????????????: /* JMP 2 mem indirect */
32'11101010?????????????????????????: /* JMP 2 direct intersegment */
32'b11111111???101??????????????????: /* JMP 2 indirect intersegment */
32'b10011111????????????????????????: /* LAHF 1 */
32'b000011110000001011??????????????: /* LAR 3 */
32'b0000111100000010????????????????: /* LAR 3 */
32'b11000101????????????????????????: /* LDS 2 */
32'b10001101????????????????????????: /* LEA 2 */
32'b11001001????????????????????????: /* LEAVE 1 */
32'b11000100????????????????????????: /* LES 2 */
32'b0000111110110100????????????????: /* LFS 3 */
32'b0000111100000001???010??????????: /* LGDT 3 */
32'b0000111110110101????????????????: /* LGS 3 */
32'b0000111100000001???011??????????: /* LLIDT 3 */
32'b000011110000000011010???????????: /* LDTR 3 from reg */
32'b0000111100000000???010??????????: /* LDTR 3 from mem */
32'b000011110000000111110???????????: /* LMSW 3 from reg */
32'b0000111100000001???110??????????: /* LMSW 3 from mem */
32'b11110000????????????????????????: /* LOCK 1 */
32'b1010110?????????????????????????: /* LODSL 1 */
32'b11100010????????????????????????: /* LOOP 2 */
32'b11100001????????????????????????: /* LOOPZ 2 */
32'b11100000????????????????????????: /* LOOPNZ 2 */
32'b000011110000001111??????????????: /* LSL 3 */
32'b0000111100000011????????????????: /* LSL 3 */
32'b0000111110110010????????????????: /* LSS 3 */
32'b000011110000000011011???????????: /* LTR 3 from reg */
32'b0000111100000000???011??????????: /* LTR 3 from mem */
32'b1000100?11??????????????????????: /* MOV 2 reg1 to reg2 */
32'b1000101?11??????????????????????: /* MOV 2 reg2 to reg1 */
32'b1000101?????????????????????????: /* MOV 2 mem to reg */
32'b1000100?????????????????????????: /* MOV 2 reg to mem */
32'b110001111000????????????????????: /* MOV 3 immediate reg */
32'b1011????????????????????????????: /* MOV 2 immediate to reg */
32'b1100011????000??????????????????: /* MOV 3 immediate to mem */
32'b1010000?????????????????????????: /* MOV 2 mem to AL,AX,EAX */
32'b1010001?????????????????????????: /* MOV 2 AL,AX,EAX to mem */
32'b000011110010001011000???????????: /* MOV 3 CRO form reg */
32'b000011110010001011010???????????: /* MOV 3 CR2 from reg */
32'b000011110010001011011???????????: /* MOV 3 CR3 from reg */
32'b000011110010001011100???????????: /* MOV 3 CR4 from reg */
32'b000011110010000011??????????????: /* MOV 3 reg form CR0-CR4 */
32'b000011110010001111??????????????: /* MOV 3 DR0-DR3 form reg */
32'b000011110010000111??????????????: /* MOV 3 reg from DR6-DR7 */
32'b1000111011??????????????????????: /* MOV 2 reg to segment reg */
32'b1000111011??????????????????????: /* MOV 2 reg to SS */
32'b10001110????????????????????????: /* MOV 2 mem to segment reg */
32'b10001110????????????????????????: /* MOV 2 memort to SS */
32'b1000110011??????????????????????: /* MOV 2 segment reg to reg */
32'b10001100????????????????????????: /* MOV 2 segment reg to mem */
32'b1010010?????????????????????????: /* MOVS 1 */
32'b000011111011111?11??????????????: /* MOVSX 3 reg2 to reg1 */
32'b000011111011111?????????????????: /* MOVSX 3 mem to reg */
32'b000011111011011?11??????????????: /* MOVZX 3 reg2 to reg1 */
32'b000011111011011?????????????????: /* MOVZX 3 mem to reg */