disasm_debug.v

使用CPLD仿真一个80383的CPU,很值得参考一下,难得

32'b1101001?11011???????????????????: begin /* RCR 2 reg by CL */
	ins_len = 2;
	$display("RCR r");
end
32'b1101001????011??????????????????: begin /* RCR 2 mem by CL */
	ins_len = 2;
	$display("RCR mem");
end
32'b1100000?11011???????????????????: begin /* RCR 3 reg by immediate */
	ins_len = 3;
	$display("RCR r,#");
end
32'b1100000????011??????????????????: begin /* RCR 3 mem by immediate */
	ins_len = 3;
	$display("RCR mem,#");
end
32'b0000111100110010????????????????: begin /* RDMSR 2 */
	ins_len = 2;
	$display("RDMSR");
end
32'b0000111100110011????????????????: begin /* RDPMC 2 */
	ins_len = 2;
	$display("RDPMC");
end
32'b0000111100110001????????????????: begin /* RDTSC 2 */
	ins_len = 2;
	$display("RDTSC");
end
32'b111100110110110?????????????????: begin /* REP INS 2 */
	ins_len = 2;
	$display("REP");
end
32'b111100111010110?????????????????: begin /* REP LODS 2 */
	ins_len = 2;
	$display("REP");
end
32'b111100111010010?????????????????: begin /* REP MOVS 2 */
	ins_len = 2;
	$display("REP");
end
32'b111100110110111?????????????????: begin /* REP OUTS 2 */
	ins_len = 2;
	$display("REP");
end
32'b111100111010101?????????????????: begin /* REP STOS 2 */
	ins_len = 2;
	$display("REP");
end
32'b111100111010011?????????????????: begin /* REP CMPS 2 */
	ins_len = 2;
	$display("REP");
end
32'b111100111010111?????????????????: begin /* REPE SCAS 2 */
	ins_len = 2;
	$display("REPE");
end
32'b111100101010011?????????????????: begin /* REPNE CMPS 2 */
	ins_len = 2;
	$display("REPNE");
end
32'b111100101010111?????????????????: begin /* REPNE SCAS 2 */
	ins_len = 2;
	$display("REPNE");
end
32'b11000011????????????????????????: begin /* RET 1 */
	ins_len = 1;
	$display("RET");
end
32'b11000010????????????????????????: begin /* RET 2 adding immediate to SP */
	ins_len = 2;
	$display("RET");
end
32'b11001011????????????????????????: begin /* RET 1 */
	ins_len = 1;
	$display("RET");
end
32'b11001010????????????????????????: begin /* RET 2 */
	ins_len = 2;
	$display("RET");
end
32'b1101000?11000???????????????????: begin /* ROL 2 reg by 1 */
	ins_len = 2;
	$display("ROL r");
end
32'b1101000????000??????????????????: begin /* ROL 2 mem by 1 */
	ins_len = 2;
	$display("ROL mem");
end
32'b1101001?11000???????????????????: begin /* ROL 2 reg by CL */
	ins_len = 2;
	$display("ROL r");
end
32'b1101001????000??????????????????: begin /* ROL 2 mem by CL */
	ins_len = 2;
	$display("ROL mem");
end
32'b1100000?11000???????????????????: begin /* ROL 2 reg by immediate */
	ins_len = 2;
	$display("ROL r");
end
32'b1100000????000??????????????????: begin /* ROL 2 mem by immediate */
	ins_len = 2;
	$display("ROL mem");
end
32'b1101000?11001???????????????????: begin /* ROR 2 reg by 1 */
	ins_len = 2;
	$display("ROR r");
end
32'b1101000????001??????????????????: begin /* ROR 2 mem by 1 */
	ins_len = 2;
	$display("ROR mem");
end
32'b1101001?11001???????????????????: begin /* ROR 2 reg by CL */
	ins_len = 2;
	$display("ROR r");
end
32'b1101001????001??????????????????: begin /* ROR 2 mem cy CL */
	ins_len = 2;
	$display("ROR mem");
end
32'b1100000?11001???????????????????: begin /* ROR 3 reg by immediate */
	ins_len = 3;
	$display("ROR r,#");
end
32'b1100000????001??????????????????: begin /* ROR 3 mem by  immediate */
	ins_len = 3;
	$display("ROR mem,#");
end
32'b0000111110101010????????????????: begin /* RSM 2 */
	ins_len = 2;
	$display("RSM");
end
32'b10011110????????????????????????: begin /* SAHF 1 */
	ins_len = 1;
	$display("SAHF");
end
32'b1101000?11111???????????????????: begin /* SAR 2 reg by 1 */
	ins_len = 2;
	$display("SAR r");
end
32'b1101000????111??????????????????: begin /* SAR 2 mem by 1 */
	ins_len = 2;
	$display("SAR mem");
end
32'b1101001?11111???????????????????: begin /* SAR 2 reg by CL */
	ins_len = 2;
	$display("SAR r");
end
32'b1101001????111??????????????????: begin /* SAR 2 mem by CL */
	ins_len = 2;
	$display("SAR mem");
end
32'b1100000?11111???????????????????: begin /* SAR 3 reg by immediate */
	ins_len = 3;
	$display("SAR r,#");
end
32'b1100000????111??????????????????: begin /* SAR 3 mem by immediate */
	ins_len = 3;
	$display("SAR mem,#");
end
32'b0001100?11??????????????????????: begin /* SBB 2 reg1 to reg2 */
	ins_len = 2;
	$display("SBB r1,r2");
end
32'b0001101?11??????????????????????: begin /* SBB 2 reg2 to reg1 */
	ins_len = 2;
	$display("SBB r2,r1");
end
32'b0001101?????????????????????????: begin /* SBB 2 mem to reg */
	ins_len = 2;
	$display("SBB mem,r");
end
32'b0001100?????????????????????????: begin /* SBB 2 reg to mem */
	ins_len = 2;
	$display("SBB r,mem");
end
32'b100000??11011???????????????????: begin /* SBB 3 immediate to reg */
	ins_len = 3;
	$display("SBB #,r");
end
32'b0001110?????????????????????????: begin /* SBB 2 immediate to AL,AX,EAX */
	ins_len = 2;
	$display("SBB #,EAX");
end
32'b100000?????011??????????????????: begin /* SBB 3 immediate to mem */
	ins_len = 3;
	$display("SBB #,mem");
end
32'b1010111?????????????????????????: begin /* SCAS 1 */
	ins_len = 1;
	$display("SCAS");
end
32'b000011111001????11000???????????: begin /* SETcc 3 reg */
	ins_len = 3;
	$display("SETcc r");
end
32'b000011111001???????000??????????: begin /* SETcc 3 mem */
	ins_len = 3;
	$display("SETcc mem");
end
32'b0000111100000001???000??????????: begin /* SGDT 3 */
	ins_len = 3;
	$display("SGDT");
end
32'b1101000?11100???????????????????: begin /* SHL 2 reg by 1 */
	ins_len = 2;
	$display("SHL r");
end
32'b1101000????100??????????????????: begin /* SHL 2 mem by 1 */
	ins_len = 2;
	$display("SHL mem");
end
32'b1101001?11100???????????????????: begin /* SHL 2 reg by CL */
	ins_len = 2;
	$display("SHL r");
end
32'b1101001????100??????????????????: begin /* SHL 2 mem by CL */
	ins_len = 2;
	$display("SHL mem");
end
32'b1100000?1100????????????????????: begin /* SHL 3 reg by immediate */
	ins_len = 3;
	$display("SHL r");
end
32'b1100000????100??????????????????: begin /* SHL 3 mem by immediate */
	ins_len = 3;
	$display("SHL mem");
end
32'b000011111010010011??????????????: begin /* SHLD 4 reg by immediate */
	ins_len = 4;
	$display("SHLD r,#");
end
32'b0000111110100100????????????????: begin /* SHLD 4 mem by immediate */
	ins_len = 4;
	$display("SHLD mem,#");
end
32'b000011111010010111??????????????: begin /* SHLD 3 reg by CL */
	ins_len = 3;
	$display("SHLD r");
end
32'b0000111110100101????????????????: begin /* SHLD 3 mem by CL */
	ins_len = 3;
	$display("SHLD mem");
end
32'b1101000?11101???????????????????: begin /* SHR 2 reg by 1 */
	ins_len = 2;
	$display("SHR r");
end
32'b1101000????101??????????????????: begin /* SHR 2 mem by 1 */
	ins_len = 2;
	$display("SHR mem");
end
32'b1101001?11101???????????????????: begin /* SHR 2 reg by CL */
	ins_len = 2;
	$display("SHR r");
end
32'b1101001????101??????????????????: begin /* SHR 2 mem by CL */
	ins_len = 2;
	$display("SHR mem");
end
32'b1100000?11101???????????????????: begin /* SHR 3 reg by immediate */
	ins_len = 3;
	$display("SHR r,#");
end
32'b1100000????101??????????????????: begin /* SHR 3 mem by immediate */
	ins_len = 3;
	$display("SHR mem,#");
end
32'b000011111010110011??????????????: begin /* SHRD 4 reg by immediate */
	ins_len = 4;
	$display("SHRD r,#");
end
32'b0000111110101100????????????????: begin /* SHRD 4 mem by immediate */
	ins_len = 4;
	$display("SHRD mem,#");
end
32'b000011111010110111??????????????: begin /* SHRD 3 reg by CL */
	ins_len = 3;
	$display("SHRD r");
end
32'b0000111110101101????????????????: begin /* SHRD 3 mem by CL */
	ins_len = 3;
	$display("SHRD mem");
end
32'b0000111100000001???001??????????: begin /* SIDT 3 */
	ins_len = 3;
	$display("SIDT");
end
32'b000011110000000011000???????????: begin /* SLDT 3 to reg */
	ins_len = 3;
	$display("SLDT r");
end
32'b0000111100000000???000??????????: begin /* SLDT 3 to mem */
	ins_len = 3;
	$display("SLDT mem");
end
32'b000011110000000111100???????????: begin /* SMSW 3 to reg */
	ins_len = 3;
	$display("SMSW r");
end
32'b0000111100000001???100??????????: begin /* SMSW 3 to mem */
	ins_len = 3;
	$display("SMSW mem");
end
32'b11111001????????????????????????: begin /* STC 1 */
	ins_len = 1;
	$display("STC");
end
32'b11111101????????????????????????: begin /* STD 1 */
	ins_len = 1;
	$display("STD");
end
32'b11111011????????????????????????: begin /* STI 1 */
	ins_len = 1;
	$display("STI");
end
32'b1010101?????????????????????????: begin /* STOS 1 */
	ins_len = 1;
	$display("STOS");
end
32'b000011110000000011001???????????: begin /* STR 3 to reg */
	ins_len = 3;
	$display("STR r");
end
32'b0000111100000000???001??????????: begin /* STR 3 to mem */
	ins_len = 3;
	$display("STR mem");
end
32'b0010100?11??????????????????????: begin /* SUB 2 reg1 to reg2 */
	ins_len = 2;
	$display("SUB r1,r2");
end
32'b0010101?11??????????????????????: begin /* SUB 2 reg2 to reg1 */
	ins_len = 2;
	$display("SUB r2,r1");
end
32'b0010101?????????????????????????: begin /* SUB 2 mem to reg */
	ins_len = 2;
	$display("SUB mem,r");
end
32'b0010100?????????????????????????: begin /* SUB 2 reg to mem */
	ins_len = 2;
	$display("SUB r,mem");
end
32'b100000??11101???????????????????: begin /* SUB 3 immediate to reg */
	ins_len = 3;
	$display("SUB #,r");
end
32'b0010110?????????????????????????: begin /* SUB 2 immediate to AL,AX,EAX */
	ins_len = 2;
	$display("SUB #,EAX");
end
32'b100000?????101??????????????????: begin /* SUB 3 immediate to mem */
	ins_len = 3;
	$display("SUB #,mem");
end
32'b1000010?11??????????????????????: begin /* TEST 2 reg1 and reg2 */
	ins_len = 2;
	$display("TEST r1,r2");
end
32'b1000010?????????????????????????: begin /* TEST 2 mem and reg */
	ins_len = 2;
	$display("TEST mem,r");
end
32'b1111011?11000???????????????????: begin /* TEST 3 immediate and reg */
	ins_len = 3;
	$display("TEST #,r");
end
32'b1010100?????????????????????????: begin /* TEST 2 immediate and AL,AX,EAX */
	ins_len = 2;
	$display("TEST #,EAX");
end
32'b1111011????000??????????????????: begin /* TEST 3 immedaite and mem */
	ins_len = 3;
	$display("TEST #,mem");
end
32'b000011110000000011100???????????: begin /* VERRR 3 reg */
	ins_len = 3;
	$display("VERRR r");
end
32'b0000111100000000???100??????????: begin /* VERRR 3 reg */
	ins_len = 3;
	$display("VERRR r");
end
32'b000011110000000011101???????????: begin /* VERW 3 reg */
	ins_len = 3;
	$display("VERW r");
end
32'b0000111100000000???101??????????: begin /* VERW 3 mem */
	ins_len = 3;
	$display("VERW mem");
end
32'b10011011????????????????????????: begin /* WAIT 1 */
	ins_len = 1;
	$display("WAIT");
end
32'b0000111100001001????????????????: begin /* WBINVD 2 */
	ins_len = 2;
	$display("WBINVD");
end
32'b0000111100110000????????????????: begin /* WRMSR 2 */
	ins_len = 2;
	$display("WRMSR");
end
32'b000011111100000?11??????????????: begin /* XADD 3 reg1,reg2 */
	ins_len = 3;
	$display("XADD r1,r2");
end
32'b000011111100000?????????????????: begin /* XADD 3 mem,reg */
	ins_len = 3;
	$display("XADD mem,r");
end
32'b1000011?11??????????????????????: begin /* XCHG 2 reg1 with reg2 */
	ins_len = 2;
	$display("XCHG r1,r2");
end
32'b10010???????????????????????????: begin /* XCHG 1 AX,EAX with reg */
	ins_len = 1;
	$display("XCHG EAX,r");
end
32'b1000011?????????????????????????: begin /* XCHG 2 mem with reg */
	ins_len = 2;
	$display("XCHG mem,r");
end
32'b11010111????????????????????????: begin /* XLAT 1 */
	ins_len = 1;
	$display("XLAT");
end
32'b0011000?11??????????????????????: begin /* XOR 2 reg1 to reg2 */
	ins_len = 2;
	$display("XOR r1,r2");
end
32'b0011001?11??????????????????????: begin /* XOR 2 reg2 to reg1 */
	ins_len = 2;
	$display("XOR r2,r1");
end
32'b0011001?????????????????????????: begin /* XOR 2 mem to reg */
	ins_len = 2;
	$display("XOR mem,r");
end
32'b0011000?????????????????????????: begin /* XOR 2 reg to mem */
	ins_len = 2;
	$display("XOR r,mem");
end
32'b100000??11110???????????????????: begin /* XOR 3 immediate to reg */
	ins_len = 3;
	$display("XOR #,r");
end
32'b0011010?????????????????????????: begin /* XOR 2 immediate to AL,AX,EAX */
	ins_len = 2;
	$display("XOR #,EAX");
end
32'b100000?????110??????????????????: begin /* XOR 3 immediate to mem */
	ins_len = 3;
	$display("XOR #,mem");
end
default: begin /* undef ins */
	ins_len = 1;
	$display("undef ins");
end
//32'b0000ffff00001011 /* UD2 */
endcase
end

endmodule