jiaozhi.vhd

通过VHDL实现汉明码

library ieee;
use ieee.std_logic_1164.all;
entity jiaozhi is
port(clk,fast_clk:			in std_logic;
	 bit_clk:			in std_logic;
	 frame_clk:			in std_logic;
	 in_data:			in std_logic_vector(11 downto 0);
	 bit_out:			out std_logic;
	 fast_out:			out std_logic;
         out_data:			out std_logic_vector(4 downto 0));
end entity jiaozhi;
architecture one of jiaozhi is
signal matrix1_0:			std_logic_vector(4 downto 0);
signal matrix1_1:			std_logic_vector(4 downto 0);
signal matrix1_2:			std_logic_vector(4 downto 0);
signal matrix1_3:			std_logic_vector(4 downto 0);
signal matrix1_4:			std_logic_vector(4 downto 0);
signal matrix1_5:			std_logic_vector(4 downto 0);
signal matrix1_6:			std_logic_vector(4 downto 0);
signal matrix1_7:			std_logic_vector(4 downto 0);
signal matrix1_8:			std_logic_vector(4 downto 0);
signal matrix1_9:			std_logic_vector(4 downto 0);
signal matrix1_10:			std_logic_vector(4 downto 0);
signal matrix1_11:			std_logic_vector(4 downto 0);

signal matrix2_0:			std_logic_vector(4 downto 0);
signal matrix2_1:			std_logic_vector(4 downto 0);
signal matrix2_2:			std_logic_vector(4 downto 0);
signal matrix2_3:			std_logic_vector(4 downto 0);
signal matrix2_4:			std_logic_vector(4 downto 0);
signal matrix2_5:			std_logic_vector(4 downto 0);
signal matrix2_6:			std_logic_vector(4 downto 0);
signal matrix2_7:			std_logic_vector(4 downto 0);
signal matrix2_8:			std_logic_vector(4 downto 0);
signal matrix2_9:			std_logic_vector(4 downto 0);
signal matrix2_10:			std_logic_vector(4 downto 0);
signal matrix2_11:			std_logic_vector(4 downto 0);
signal flag:				std_logic;
signal count5,count5_1,count5_2:		integer range 0 to 4;
signal count12:					integer range 0 to 11;
begin

fast_out<=fast_clk;

process(frame_clk)
    begin
	if frame_clk'event and frame_clk='1' then
	flag<=not flag;
	end if;
	end process;
	
	
counter: process(bit_clk,frame_clk)
	begin
	if bit_clk'event and bit_clk='1' then
	count5_1<=count5_1+1;
    if frame_clk='1' then
	count5_1<=0;
	end if;
	end if;
end process;
datain:process(bit_clk)
begin
if bit_clk'event and bit_clk='1' then
case flag is
   	WHEN '0' =>  matrix1_0(count5_1)<=in_data(0);
		     matrix1_1(count5_1)<=in_data(1);
		     matrix1_2(count5_1)<=in_data(2);
		     matrix1_3(count5_1)<=in_data(3);
		     matrix1_4(count5_1)<=in_data(4);
		     matrix1_5(count5_1)<=in_data(5);
		     matrix1_6(count5_1)<=in_data(6);
		     matrix1_7(count5_1)<=in_data(7);
		     matrix1_8(count5_1)<=in_data(8);
		     matrix1_9(count5_1)<=in_data(9);
		     matrix1_10(count5_1)<=in_data(10);
		     matrix1_11(count5_1)<=in_data(11);
				
   	WHEN '1' =>  matrix2_0(count5_1)<=in_data(0);
		     matrix2_1(count5_1)<=in_data(1);
		     matrix2_2(count5_1)<=in_data(2);
		     matrix2_3(count5_1)<=in_data(3);
		     matrix2_4(count5_1)<=in_data(4);
		     matrix2_5(count5_1)<=in_data(5);
		     matrix2_6(count5_1)<=in_data(6);
		     matrix2_7(count5_1)<=in_data(7);
		     matrix2_8(count5_1)<=in_data(8);
		     matrix2_9(count5_1)<=in_data(9);
		     matrix2_10(count5_1)<=in_data(10);
		     matrix2_11(count5_1)<=in_data(11);
  	WHEN OTHERS =>
                     null;
   END CASE;
end if;
end process;

dataout:process(fast_clk,frame_clk)
	begin
	if frame_clk='1' then
	count12<=0;
	count5_2<=0;
	elsif fast_clk'event and fast_clk='1' then
	if count5_2=4 then 
	count5_2<=0;
		if count12=11 then
		count12<=0;
		else
		count12<=count12+1;
		end if;
	else
	count5_2<=count5_2+1;
	end if;
	if flag='0' then
		case count12 is
		when 0=>out_data<=matrix2_0;
		when 1=>out_data<=matrix2_1;
		when 2=>out_data<=matrix2_2;
		when 3=>out_data<=matrix2_3;
		when 4=>out_data<=matrix2_4;
		when 5=>out_data<=matrix2_5;
		when 6=>out_data<=matrix2_6;
		when 7=>out_data<=matrix2_7;
		when 8=>out_data<=matrix2_8;
		when 9=>out_data<=matrix2_9;
		when 10=>out_data<=matrix2_10;
		when 11=>out_data<=matrix2_11;
		when others=>null;
		end case;	
	else
		case count12 is
		when 0=>out_data<=matrix1_0;
		when 1=>out_data<=matrix1_1;
		when 2=>out_data<=matrix1_2;
		when 3=>out_data<=matrix1_3;
		when 4=>out_data<=matrix1_4;
		when 5=>out_data<=matrix1_5;
		when 6=>out_data<=matrix1_6;
		when 7=>out_data<=matrix1_7;
		when 8=>out_data<=matrix1_8;
		when 9=>out_data<=matrix1_9;
		when 10=>out_data<=matrix1_10;
		when 11=>out_data<=matrix1_11;
		when others=>null;
		end case;	
	end if;	
	if count5_2=1 then
		bit_out<='1';
		else
		bit_out<='0';
	end if;
end if;

end process;
end architecture one ;