hamming.vhd

通过VHDL实现汉明码

library ieee;
use ieee.std_logic_1164.all;
entity hamming is
port(clk:				in std_logic;
     bit_clk:				in std_logic;
     frame_clk:				in std_logic;
     in_data:				in std_logic;
     out_data:				out std_logic_vector(11 downto 0));
end entity hamming;
architecture one of hamming is
signal m:				std_logic_vector(7 downto 0);
begin
code:process(clk)
begin
if clk'event and clk='1'
  then 
	m(7 downto 1)<=m(6 downto 0);
        m(0)<=in_data;
end if;
end process;
dataout:process(bit_clk)
begin
if bit_clk'event and bit_clk='1' then
	   out_data(11 downto 4)<=m;
	   out_data(0)<=m(2) xor m(3) xor m(5) xor m(6) xor m(7);
	   out_data(1)<=m(1) xor m(3) xor m(4) xor m(6) xor m(7);
	   out_data(2)<=m(0) xor m(1) xor m(4) xor m(5) xor m(7);
	   out_data(3)<=m(0) xor m(2) xor m(4) xor m(5) xor m(6);
end if;
end process;
end architecture one ;