jiehamming.vhd

通过VHDL实现汉明码

library ieee;
use ieee.std_logic_1164.all;
entity jiehamming is
port(clk:				in std_logic;
     bit_clk:				in std_logic;
     frame_clk:				in std_logic;
     in_data:				in std_logic;
     out_data:				out std_logic;
end entity jiehamming;
architecture one of jiehamming is
signal m:				std_logic_vector(11 downto 0);
signal s1,s2,s3,s4   			integer range (1 downto 0)
begin
process(bit_clk)
begin
if clk'event and clk='1'
  then 
	m(11 downto 1)<=m(10 downto 0);
        m(0)<=in_data;
end if;
end process;
process(bit_clk)
begin
if bit_clk'event and bit_clk='1' then

	   s1<=m(2) xor m(3) xor m(5) xor m(6) xor m(7);
	   s2<=m(1) xor m(3) xor m(4) xor m(6) xor m(7);
	   s3<=m(0) xor m(1) xor m(4) xor m(5) xor m(7);
	   s4<=m(0) xor m(2) xor m(4) xor m(5) xor m(6);
case s1s2s3s4 is
           when '1000'=> m(0)<=m(0)xor'1';
           when '0100'=> m(1)<=m(1)xor'1';
           when '0010'=> m(2)<=m(2)xor'1';
	   when '0001'=> m(3)<=m(3)xor'1';
	   when '0011'=> m(4)<=m(4)xor'1';
           when '1100'=> m(5)<=m(5)xor'1';
	   when '1001'=> m(6)<=m(6)xor'1';
	   when '0110'=> m(7)<=m(7)xor'1';
	   when '0111'=> m(8)<=m(8)xor'1';
	   when '1011'=> m(9)<=m(9)xor'1';
	   when '1101'=> m(10)<=m(10)xor'1';
	   when '1110'=> m(11)<=m(11)xor'1';
end case
           out_data(7 downto 0)<=m(11 downto 4)	   
end if;
end process;
end architecture one ;