c8255.vhd

基于vhdl的8255A的设计与分析

LIBRARY IEEE;

 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.STD_LOGIC_ARITH.ALL;
 USE IEEE.STD_LOGIC_UNSIGNED.ALL;


ENTITY  c8255 IS
  PORT(reset, rd, wr, cs, a0, a1:IN STD_ULOGIC;   
       Pa:INOUT STD_ULOGIC_VECTOR(7 DOWNTO 0);
       Pb:INOUT STD_ULOGIC_VECTOR(7 DOWNTO 0);
  	   Pcl:INOUT STD_ULOGIC_VECTOR(3 DOWNTO 0);
  	   Pch:INOUT STD_ULOGIC_VECTOR(3 DOWNTO 0);
  	  d:INOUT STD_ULOGIC_VECTOR(7 DOWNTO 0));
  END c8255;


ARCHITECTURE test OF c8255 IS
   SIGNAL internal_bus_out:STD_ULOGIC_VECTOR(7 DOWNTO 0);
   SIGNAL internal_bus_in:STD_ULOGIC_VECTOR(7 DOWNTO 0);
   SIGNAL flag:STD_ULOGIC_VECTOR(1 DOWNTO 0);
   SIGNAL ctrreg:STD_ULOGIC_VECTOR(7 DOWNTO 0); 
   SIGNAL Pa_latch, Pb_latch, Pc_latch:STD_ULOGIC_VECTOR(7 DOWNTO 0); 


BEGIN

  read:PROCESS(rd,cs)
    BEGIN
        IF(cs='0'AND rd='0')THEN
        IF(a0='0'AND a1='0'AND ctrreg(4)='1')THEN
        internal_bus_in<=Pa;
      
       ELSIF(a0='0'AND a1='1'AND ctrreg(3)='1' and ctrreg(0)='0')THEN 
          internal_bus_in(7 DOWNTO 4)<=Pch(3 DOWNTO 0);

       ELSIF(a0='0'AND a1='1'AND ctrreg(3)='0' and ctrreg(0)='1')THEN 
          internal_bus_in(3 DOWNTO 0)<=Pcl(3 DOWNTO 0);

       ELSIF(a0='1'AND a1='0'AND ctrreg(1)='1')THEN 
          internal_bus_in<=Pb;

	   ELSIF(a0='0'AND a1='1'AND ctrreg(3)='0' and ctrreg(0)='1' AND ctrreg(7)='1')THEN 
		  internal_bus_in(3 DOWNTO 0)<=Pcl(3 DOWNTO 0);
		  internal_bus_in(7 DOWNTO 4)<=Pch(3 DOWNTO 0);
		END IF;

	 ELSE 
	     internal_bus_in<="ZZZZZZZZ";

	END IF;
	     d<= internal_bus_in;

	END PROCESS;



res:PROCESS(cs,wr,reset)
	  VARIABLE ctrregf:STD_ULOGIC;
	  VARIABLE bctrreg_v:STD_ULOGIC_VECTOR(3 DOWNTO 0);

 BEGIN
	IF(cs='0' AND wr='0') THEN
	ctrregf:=d(7);
	internal_bus_out<=d;
	END IF;

	IF(reset='1')THEN
    bctrreg_v:="0000";    
	Pa_latch<="00000000";
	Pb_latch<="00000000";
	Pc_latch<="00000000";
	  ctrreg<="10111011"; 
	 ctrregf:='0';
	 ELSIF(wr'EVENT AND wr='1') THEN
	    IF(ctrregf='1' AND a1='1' and a0='1' AND cs='0') THEN
	      ctrreg<=internal_bus_out;
	  ELSIF(ctrreg(7)='1' AND cs='0' AND a1='0' and a0='0') THEN
	      Pa_latch<=internal_bus_out;
	  ELSIF(ctrreg(7)='1' AND cs='0' AND a1='0' and a0='1') THEN
	      Pb_latch<=internal_bus_out;
      ELSIF(ctrreg(7)='1' AND cs='0' AND a1='1' and a0='0') THEN
	      Pc_latch<=internal_bus_out; 
	 	END IF;

	IF (ctrregf='0'AND cs='0'AND a1='1' and a0='1') THEN
	  bctrreg_v:=internal_bus_out(3 DOWNTO 0);

	CASE  bctrreg_v IS
	 WHEN "0000" => Pc_latch(0)<='0';
	 WHEN "0010" => Pc_latch(1)<='0';
	 WHEN "0100" => Pc_latch(2)<='0';
	 WHEN "0110" => Pc_latch(3)<='0';
	 WHEN "1000" => Pc_latch(4)<='0';
	 WHEN "1010" => Pc_latch(5)<='0';
	 WHEN "1100" => Pc_latch(6)<='0';
	 WHEN "1110" => Pc_latch(7)<='0';
	 WHEN "0001" => Pc_latch(0)<='0';
	 WHEN "0011" => Pc_latch(1)<='0';
	 WHEN "0101" => Pc_latch(2)<='0';
	 WHEN "0111" => Pc_latch(3)<='0';
	 WHEN "1001" => Pc_latch(4)<='0';
	 WHEN "1011" => Pc_latch(5)<='0';
	 WHEN "1101" => Pc_latch(6)<='0';
	 WHEN "1111" => Pc_latch(7)<='0';
	  WHEN OTHERS=> flag<="11";
	END CASE;

	END IF;
	END IF;

END PROCESS res;


Pakou:PROCESS(Pa_latch)
   BEGIN
      IF(ctrreg(4)='0') THEN
       Pa<=(Pa_latch);
      ELSE
       Pa<="ZZZZZZZZ";
       END IF;
    END  PROCESS pakou;


Pbkou: PROCESS(Pb_latch)
   BEGIN
      IF(ctrreg(1)='0') THEN
       Pb<=Pb_latch;
      ELSE
       Pb<="ZZZZZZZZ";
       END IF;
    END  PROCESS Pbkou;


Pclkou: PROCESS(Pc_latch)
   BEGIN
      IF(ctrreg(0)='0') THEN
       PcL<=Pc_latch(3 DOWNTO 0);
      ELSE
       Pcl<="ZZZZ";
       END IF;
    END  PROCESS Pclkou;


Pchkou: PROCESS(Pc_latch)
   BEGIN
      IF(ctrreg(3)='0') THEN
       Pch<=Pc_latch(7 DOWNTO 4);
      ELSE
       Pch<="ZZZZ";
       END IF;
    END  PROCESS Pchkou;
 END test;