c8255.rpt

基于vhdl的8255A的设计与分析

         # !a1 & !cs & !Pa4 & !Pb4 &  ~PIN002 &  ~PIN004 & !rd &  _X017 & 
              _X018 &  _X019 &  _X020
         # !a1 & !cs & !d4 & !Pb4 & !~PIN002 &  ~PIN004 & !rd &  _X017 & 
              _X018 &  _X019 &  _X020
         # !a0 & !a1 & !cs & !d4 & !Pa4 & !rd &  _X017 &  _X018 &  _X019 & 
              _X020;
  _X017  = EXP( a0 &  a1 & !d4);
  _X018  = EXP( a1 & !d4 &  ~PIN006);
  _X019  = EXP( a0 & !d4 & !~PIN004);
  _X020  = EXP( a1 & !d4 & !~PIN008);

-- Node name is 'd4~2' 
-- Equation name is 'd4~2', location is LC032, type is buried.
-- synthesized logic cell 
_LC032   = LCELL( _EQ019 $  GND);
  _EQ019 = !a0 & !a1 & !cs & !d4 & !~PIN002 & !rd &  _X017 &  _X018 &  _X019 & 
              _X020
         #  _LC026;
  _X017  = EXP( a0 &  a1 & !d4);
  _X018  = EXP( a1 & !d4 &  ~PIN006);
  _X019  = EXP( a0 & !d4 & !~PIN004);
  _X020  = EXP( a1 & !d4 & !~PIN008);

-- Node name is 'd4' 
-- Equation name is 'd4', location is LC019, type is bidir.
d4       = TRI(_LC019, GLOBAL(!~PIN009));
_LC019   = LCELL( _EQ020 $  _EQ021);
  _EQ020 = !a0 &  a1 & !cs & !Pch0 & !~PIN006 &  ~PIN008 & !rd &  _X017 & 
              _X018 &  _X019 &  _X020
         #  a0 & !a1 & !cs & !Pb4 &  ~PIN004 & !rd &  _X017 &  _X018 &  _X019 & 
              _X020
         # !a0 & !a1 & !cs & !Pa4 &  ~PIN002 & !rd &  _X017 &  _X018 &  _X019 & 
              _X020
         #  _LC032;
  _X017  = EXP( a0 &  a1 & !d4);
  _X018  = EXP( a1 & !d4 &  ~PIN006);
  _X019  = EXP( a0 & !d4 & !~PIN004);
  _X020  = EXP( a1 & !d4 & !~PIN008);
  _EQ021 = !cs & !rd &  _X017 &  _X018 &  _X019 &  _X020;
  _X017  = EXP( a0 &  a1 & !d4);
  _X018  = EXP( a1 & !d4 &  ~PIN006);
  _X019  = EXP( a0 & !d4 & !~PIN004);
  _X020  = EXP( a1 & !d4 & !~PIN008);

-- Node name is 'd5~1' 
-- Equation name is 'd5~1', location is LC036, type is buried.
-- synthesized logic cell 
_LC036   = LCELL( _EQ022 $  GND);
  _EQ022 = !a0 & !cs & !Pa5 & !Pch1 &  ~PIN002 & !~PIN006 &  ~PIN008 & !rd & 
              _X021 &  _X022 &  _X023 &  _X024
         # !a0 & !cs & !d5 & !Pch1 & !~PIN002 & !~PIN006 &  ~PIN008 & !rd & 
              _X021 &  _X022 &  _X023 &  _X024
         # !a1 & !cs & !Pa5 & !Pb5 &  ~PIN002 &  ~PIN004 & !rd &  _X021 & 
              _X022 &  _X023 &  _X024
         # !a1 & !cs & !d5 & !Pb5 & !~PIN002 &  ~PIN004 & !rd &  _X021 & 
              _X022 &  _X023 &  _X024
         # !a0 & !a1 & !cs & !d5 & !Pa5 & !rd &  _X021 &  _X022 &  _X023 & 
              _X024;
  _X021  = EXP( a0 &  a1 & !d5);
  _X022  = EXP( a1 & !d5 &  ~PIN006);
  _X023  = EXP( a0 & !d5 & !~PIN004);
  _X024  = EXP( a1 & !d5 & !~PIN008);

-- Node name is 'd5~2' 
-- Equation name is 'd5~2', location is LC045, type is buried.
-- synthesized logic cell 
_LC045   = LCELL( _EQ023 $  GND);
  _EQ023 = !a0 & !a1 & !cs & !d5 & !~PIN002 & !rd &  _X021 &  _X022 &  _X023 & 
              _X024
         #  _LC036;
  _X021  = EXP( a0 &  a1 & !d5);
  _X022  = EXP( a1 & !d5 &  ~PIN006);
  _X023  = EXP( a0 & !d5 & !~PIN004);
  _X024  = EXP( a1 & !d5 & !~PIN008);

-- Node name is 'd5' 
-- Equation name is 'd5', location is LC040, type is bidir.
d5       = TRI(_LC040, GLOBAL(!~PIN009));
_LC040   = LCELL( _EQ024 $  _EQ025);
  _EQ024 = !a0 &  a1 & !cs & !Pch1 & !~PIN006 &  ~PIN008 & !rd &  _X021 & 
              _X022 &  _X023 &  _X024
         #  a0 & !a1 & !cs & !Pb5 &  ~PIN004 & !rd &  _X021 &  _X022 &  _X023 & 
              _X024
         # !a0 & !a1 & !cs & !Pa5 &  ~PIN002 & !rd &  _X021 &  _X022 &  _X023 & 
              _X024
         #  _LC045;
  _X021  = EXP( a0 &  a1 & !d5);
  _X022  = EXP( a1 & !d5 &  ~PIN006);
  _X023  = EXP( a0 & !d5 & !~PIN004);
  _X024  = EXP( a1 & !d5 & !~PIN008);
  _EQ025 = !cs & !rd &  _X021 &  _X022 &  _X023 &  _X024;
  _X021  = EXP( a0 &  a1 & !d5);
  _X022  = EXP( a1 & !d5 &  ~PIN006);
  _X023  = EXP( a0 & !d5 & !~PIN004);
  _X024  = EXP( a1 & !d5 & !~PIN008);

-- Node name is 'd6~1' 
-- Equation name is 'd6~1', location is LC007, type is buried.
-- synthesized logic cell 
_LC007   = LCELL( _EQ026 $  GND);
  _EQ026 = !a0 & !cs & !Pa6 & !Pch2 &  ~PIN002 & !~PIN006 &  ~PIN008 & !rd & 
              _X025 &  _X026 &  _X027 &  _X028
         # !a0 & !cs & !d6 & !Pch2 & !~PIN002 & !~PIN006 &  ~PIN008 & !rd & 
              _X025 &  _X026 &  _X027 &  _X028
         # !a1 & !cs & !Pa6 & !Pb6 &  ~PIN002 &  ~PIN004 & !rd &  _X025 & 
              _X026 &  _X027 &  _X028
         # !a1 & !cs & !d6 & !Pb6 & !~PIN002 &  ~PIN004 & !rd &  _X025 & 
              _X026 &  _X027 &  _X028
         # !a0 & !a1 & !cs & !d6 & !Pa6 & !rd &  _X025 &  _X026 &  _X027 & 
              _X028;
  _X025  = EXP( a0 &  a1 & !d6);
  _X026  = EXP( a1 & !d6 &  ~PIN006);
  _X027  = EXP( a0 & !d6 & !~PIN004);
  _X028  = EXP( a1 & !d6 & !~PIN008);

-- Node name is 'd6~2' 
-- Equation name is 'd6~2', location is LC004, type is buried.
-- synthesized logic cell 
_LC004   = LCELL( _EQ027 $  GND);
  _EQ027 = !a0 & !a1 & !cs & !d6 & !~PIN002 & !rd &  _X025 &  _X026 &  _X027 & 
              _X028
         #  _LC007;
  _X025  = EXP( a0 &  a1 & !d6);
  _X026  = EXP( a1 & !d6 &  ~PIN006);
  _X027  = EXP( a0 & !d6 & !~PIN004);
  _X028  = EXP( a1 & !d6 & !~PIN008);

-- Node name is 'd6' 
-- Equation name is 'd6', location is LC001, type is bidir.
d6       = TRI(_LC001, GLOBAL(!~PIN009));
_LC001   = LCELL( _EQ028 $  _EQ029);
  _EQ028 = !a0 &  a1 & !cs & !Pch2 & !~PIN006 &  ~PIN008 & !rd &  _X025 & 
              _X026 &  _X027 &  _X028
         #  a0 & !a1 & !cs & !Pb6 &  ~PIN004 & !rd &  _X025 &  _X026 &  _X027 & 
              _X028
         # !a0 & !a1 & !cs & !Pa6 &  ~PIN002 & !rd &  _X025 &  _X026 &  _X027 & 
              _X028
         #  _LC004;
  _X025  = EXP( a0 &  a1 & !d6);
  _X026  = EXP( a1 & !d6 &  ~PIN006);
  _X027  = EXP( a0 & !d6 & !~PIN004);
  _X028  = EXP( a1 & !d6 & !~PIN008);
  _EQ029 = !cs & !rd &  _X025 &  _X026 &  _X027 &  _X028;
  _X025  = EXP( a0 &  a1 & !d6);
  _X026  = EXP( a1 & !d6 &  ~PIN006);
  _X027  = EXP( a0 & !d6 & !~PIN004);
  _X028  = EXP( a1 & !d6 & !~PIN008);

-- Node name is 'd7~1' 
-- Equation name is 'd7~1', location is LC006, type is buried.
-- synthesized logic cell 
_LC006   = LCELL( _EQ030 $  GND);
  _EQ030 = !a0 & !cs & !Pa7 & !Pch3 &  ~PIN002 & !~PIN006 &  ~PIN008 & !rd & 
              _X029 &  _X030 &  _X031 &  _X032
         # !a0 & !cs & !d7 & !Pch3 & !~PIN002 & !~PIN006 &  ~PIN008 & !rd & 
              _X029 &  _X030 &  _X031 &  _X032
         # !a1 & !cs & !Pa7 & !Pb7 &  ~PIN002 &  ~PIN004 & !rd &  _X029 & 
              _X030 &  _X031 &  _X032
         # !a1 & !cs & !d7 & !Pb7 & !~PIN002 &  ~PIN004 & !rd &  _X029 & 
              _X030 &  _X031 &  _X032
         # !a0 & !a1 & !cs & !d7 & !Pa7 & !rd &  _X029 &  _X030 &  _X031 & 
              _X032;
  _X029  = EXP( a0 &  a1 & !d7);
  _X030  = EXP( a1 & !d7 &  ~PIN006);
  _X031  = EXP( a0 & !d7 & !~PIN004);
  _X032  = EXP( a1 & !d7 & !~PIN008);

-- Node name is 'd7~2' 
-- Equation name is 'd7~2', location is LC078, type is buried.
-- synthesized logic cell 
_LC078   = LCELL( _EQ031 $  GND);
  _EQ031 = !a0 & !a1 & !cs & !d7 & !~PIN002 & !rd &  _X029 &  _X030 &  _X031 & 
              _X032
         #  _LC006;
  _X029  = EXP( a0 &  a1 & !d7);
  _X030  = EXP( a1 & !d7 &  ~PIN006);
  _X031  = EXP( a0 & !d7 & !~PIN004);
  _X032  = EXP( a1 & !d7 & !~PIN008);

-- Node name is 'd7' 
-- Equation name is 'd7', location is LC003, type is bidir.
d7       = TRI(_LC003, GLOBAL(!~PIN009));
_LC003   = LCELL( _EQ032 $  _EQ033);
  _EQ032 = !a0 &  a1 & !cs & !Pch3 & !~PIN006 &  ~PIN008 & !rd &  _X029 & 
              _X030 &  _X031 &  _X032
         #  a0 & !a1 & !cs & !Pb7 &  ~PIN004 & !rd &  _X029 &  _X030 &  _X031 & 
              _X032
         # !a0 & !a1 & !cs & !Pa7 &  ~PIN002 & !rd &  _X029 &  _X030 &  _X031 & 
              _X032
         #  _LC078;
  _X029  = EXP( a0 &  a1 & !d7);
  _X030  = EXP( a1 & !d7 &  ~PIN006);
  _X031  = EXP( a0 & !d7 & !~PIN004);
  _X032  = EXP( a1 & !d7 & !~PIN008);
  _EQ033 = !cs & !rd &  _X029 &  _X030 &  _X031 &  _X032;
  _X029  = EXP( a0 &  a1 & !d7);
  _X030  = EXP( a1 & !d7 &  ~PIN006);
  _X031  = EXP( a0 & !d7 & !~PIN004);
  _X032  = EXP( a1 & !d7 & !~PIN008);

-- Node name is ':70' = 'Pa_latch0' 
-- Equation name is 'Pa_latch0', location is LC094, type is output.
 Pa_latch0 = DFFE( _EQ034 $  GND, GLOBAL( wr), !reset,  VCC,  VCC);
  _EQ034 =  a0 &  a1 & !cs &  _LC071 &  Pa_latch0
         #  _LC082 &  _X033;
  _X033  = EXP( a0 &  a1 & !cs &  _LC071);

-- Node name is ':69' = 'Pa_latch1' 
-- Equation name is 'Pa_latch1', location is LC072, type is output.
 Pa_latch1 = DFFE( _EQ035 $  GND, GLOBAL( wr), !reset,  VCC,  VCC);
  _EQ035 =  a0 &  a1 & !cs &  _LC071 &  Pa_latch1
         #  _LC069 &  _X033;
  _X033  = EXP( a0 &  a1 & !cs &  _LC071);

-- Node name is ':68' = 'Pa_latch2' 
-- Equation name is 'Pa_latch2', location is LC038, type is output.
 Pa_latch2 = DFFE( _EQ036 $  GND, GLOBAL( wr), !reset,  VCC,  VCC);
  _EQ036 =  a0 &  a1 & !cs &  _LC071 &  Pa_latch2
         #  _LC039 &  _X033;
  _X033  = EXP( a0 &  a1 & !cs &  _LC071);

-- Node name is ':67' = 'Pa_latch3' 
-- Equation name is 'Pa_latch3', location is LC056, type is output.
 Pa_latch3 = DFFE( _EQ037 $  GND, GLOBAL( wr), !reset,  VCC,  VCC);
  _EQ037 =  a0 &  a1 & !cs &  _LC071 &  Pa_latch3
         #  _LC061 &  _X033;
  _X033  = EXP( a0 &  a1 & !cs &  _LC071);

-- Node name is ':66' = 'Pa_latch4' 
-- Equation name is 'Pa_latch4', location is LC073, type is output.
 Pa_latch4 = TFFE( _EQ038, GLOBAL( wr), !reset,  VCC,  VCC);
  _EQ038 = !a0 & !a1 & !cs &  ctrreg7 &  _LC074 & !Pa_latch4
         # !a0 & !a1 & !cs &  ctrreg7 & !_LC074 &  Pa_latch4;

-- Node name is ':65' = 'Pa_latch5' 
-- Equation name is 'Pa_latch5', location is LC037, type is output.
 Pa_latch5 = DFFE( _EQ039 $  GND, GLOBAL( wr), !reset,  VCC,  VCC);
  _EQ039 =  a0 &  a1 & !cs &  _LC071 &  Pa_latch5
         #  _LC047 &  _X033;
  _X033  = EXP( a0 &  a1 & !cs &  _LC071);

-- Node name is ':64' = 'Pa_latch6' 
-- Equation name is 'Pa_latch6', location is LC046, type is output.
 Pa_latch6 = DFFE( _EQ040 $  GND, GLOBAL( wr), !reset,  VCC,  VCC);
  _EQ040 =  a0 &  a1 & !cs &  _LC071 &  Pa_latch6
         #  _LC016 &  _X033;
  _X033  = EXP( a0 &  a1 & !cs &  _LC071);

-- Node name is ':63' = 'Pa_latch7' 
-- Equation name is 'Pa_latch7', location is LC057, type is output.
 Pa_latch7 = DFFE( _EQ041 $  GND, GLOBAL( wr), !reset,  VCC,  VCC);
  _EQ041 =  a0 &  a1 & !cs &  _LC071 &  Pa_latch7
         #  _LC063 &  _X033;
  _X033  = EXP( a0 &  a1 & !cs &  _LC071);

-- Node name is ':78' = 'Pb_latch0' 
-- Equation name is 'Pb_latch0', location is LC095, type is buried.
Pb_latch0 = TFFE( _EQ042, GLOBAL( wr), !reset,  VCC,  VCC);
  _EQ042 =  a0 & !a1 & !cs &  ctrreg7 &  _LC087 & !Pb_latch0
         #  a0 & !a1 & !cs &  ctrreg7 & !_LC087 &  Pb_latch0;

-- Node name is ':77' = 'Pb_latch1' 
-- Equation name is 'Pb_latch1', location is LC077, type is buried.
Pb_latch1 = TFFE( _EQ043, GLOBAL( wr), !reset,  VCC,  VCC);
  _EQ043 =  a0 & !a1 & !cs &  ctrreg7 &  _LC066 & !Pb_latch1
         #  a0 & !a1 & !cs &  ctrreg7 & !_LC066 &  Pb_latch1;

-- Node name is ':76' = 'Pb_latch2' 
-- Equation name is 'Pb_latch2', location is LC059, type is buried.
Pb_latch2 = TFFE( _EQ044, GLOBAL( wr), !reset,  VCC,  VCC);
  _EQ044 =  a0 & !a1 & !cs &  ctrreg7 &  _LC034 & !Pb_latch2
         #  a0 & !a1 & !cs &  ctrreg7 & !_LC034 &  Pb_latch2;

-- Node name is ':75' = 'Pb_latch3' 
-- Equation name is 'Pb_latch3', location is LC085, type is buried.
Pb_latch3 = TFFE( _EQ045, GLOBAL( wr), !reset,  VCC,  VCC);
  _EQ0