📄 c8255.rpt
字号:
D: LC49 - LC64 16/16(100%) 10/10(100%) 3/16( 18%) 29/36( 80%)
E: LC65 - LC80 16/16(100%) 8/10( 80%) 16/16(100%) 28/36( 77%)
F: LC81 - LC96 16/16(100%) 10/10(100%) 8/16( 50%) 30/36( 83%)
Total dedicated input pins used: 4/4 (100%)
Total I/O pins used: 57/60 ( 95%)
Total logic cells used: 78/96 ( 81%)
Total shareable expanders used: 47/96 ( 48%)
Total Turbo logic cells used: 78/96 ( 81%)
Total shareable expanders not available (n/a): 23/96 ( 23%)
Average fan-in: 8.39
Total fan-in: 655
Total input pins required: 24
Total output pins required: 21
Total bidirectional pins required: 16
Total logic cells required: 78
Total flipflops required: 29
Total product terms required: 308
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 34
Synthesized logic cells: 32/ 96 ( 33%)
Device-Specific Information: d:\a8255\c8255.rpt
c8255
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
1 - - INPUT 0 0 0 0 0 28 32 a0
12 (6) (A) INPUT 0 0 0 0 0 28 32 a1
11 (8) (A) INPUT 0 0 0 0 0 29 41 cs
70 83 F BIDIR 5 4 1 6 7 1 3 d0
57 65 E BIDIR 5 4 1 6 7 1 3 d1
41 33 C BIDIR 5 4 1 6 7 1 3 d2
28 17 B BIDIR 5 4 1 6 7 1 3 d3
27 19 B BIDIR 5 4 1 6 7 2 3 d4
35 40 C BIDIR 5 4 1 6 7 1 3 d5
16 1 A BIDIR 5 4 1 6 7 1 3 d6
15 3 A BIDIR 5 4 1 6 7 1 4 d7
20 (28) (B) INPUT s 0 0 0 0 0 1 1 Pa0
18 (29) (B) INPUT s 0 0 0 0 0 1 1 Pa1
33 (43) (C) INPUT s 0 0 0 0 0 1 1 Pa2
29 (48) (C) INPUT s 0 0 0 0 0 1 1 Pa3
8 (12) (A) INPUT s 0 0 0 0 0 1 1 Pa4
24 (22) (B) INPUT s 0 0 0 0 0 1 1 Pa5
34 (41) (C) INPUT s 0 0 0 0 0 1 1 Pa6
52 (59) (D) INPUT s 0 0 0 0 0 1 1 Pa7
25 21 B BIDIR 0 0 0 0 2 1 1 Pb0
58 67 E BIDIR 0 0 0 0 2 1 1 Pb1
23 24 B BIDIR 0 0 0 0 2 1 1 Pb2
69 81 F BIDIR 0 0 0 0 2 1 1 Pb3
22 25 B BIDIR 0 0 0 0 2 1 1 Pb4
40 35 C BIDIR 0 0 0 0 2 1 1 Pb5
45 51 D BIDIR 0 0 0 0 2 1 1 Pb6
48 53 D BIDIR 0 0 0 0 2 1 1 Pb7
60 (69) (E) INPUT s 0 0 0 0 0 1 1 Pch0
64 (75) (E) INPUT s 0 0 0 0 0 1 1 Pch1
5 (14) (A) INPUT s 0 0 0 0 0 1 1 Pch2
17 (32) (B) INPUT s 0 0 0 0 0 1 1 Pch3
4 (16) (A) INPUT s 0 0 0 0 0 1 1 Pcl0
54 (61) (D) INPUT s 0 0 0 0 0 1 1 Pcl1
31 (45) (C) INPUT s 0 0 0 0 0 1 1 Pcl2
21 (27) (B) INPUT s 0 0 0 0 0 1 1 Pcl3
84 - - INPUT G s 0 0 0 0 0 0 0 ~PIN003
2 - - INPUT G s 0 0 0 0 0 0 0 ~PIN009
10 (9) (A) INPUT 0 0 0 0 0 9 16 rd
9 (11) (A) INPUT 0 0 0 0 0 20 10 reset
83 - - INPUT G 0 0 0 0 0 1 9 wr
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\a8255\c8255.rpt
c8255
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
70 83 F TRI t 5 4 1 6 7 1 3 d0
57 65 E TRI t 5 4 1 6 7 1 3 d1
41 33 C TRI t 5 4 1 6 7 1 3 d2
28 17 B TRI t 5 4 1 6 7 1 3 d3
27 19 B TRI t 5 4 1 6 7 2 3 d4
35 40 C TRI t 5 4 1 6 7 1 3 d5
16 1 A TRI t 5 4 1 6 7 1 3 d6
15 3 A TRI t 5 4 1 6 7 1 4 d7
80 94 F FF + t 1 1 0 4 3 1 1 Pa_latch0 (:70)
62 72 E FF + t 1 1 0 4 3 1 1 Pa_latch1 (:69)
36 38 C FF + t 1 1 0 4 3 1 1 Pa_latch2 (:68)
50 56 D FF + t 1 1 0 4 3 1 1 Pa_latch3 (:67)
63 73 E FF + t 0 0 0 4 3 1 0 Pa_latch4 (:66)
37 37 C FF + t 1 1 0 4 3 1 1 Pa_latch5 (:65)
30 46 C FF + t 1 1 0 4 3 1 1 Pa_latch6 (:64)
51 57 D FF + t 1 1 0 4 3 1 1 Pa_latch7 (:63)
25 21 B TRI t 0 0 0 0 2 1 1 Pb0
58 67 E TRI t 0 0 0 0 2 1 1 Pb1
23 24 B TRI t 0 0 0 0 2 1 1 Pb2
69 81 F TRI t 0 0 0 0 2 1 1 Pb3
22 25 B TRI t 0 0 0 0 2 1 1 Pb4
40 35 C TRI t 0 0 0 0 2 1 1 Pb5
45 51 D TRI t 0 0 0 0 2 1 1 Pb6
48 53 D TRI t 0 0 0 0 2 1 1 Pb7
71 84 F FF + t 0 0 0 4 7 1 0 Pc_latch0 (:86)
74 88 F FF + t 0 0 0 4 6 1 0 Pc_latch1 (:85)
81 96 F FF + t 0 0 0 4 6 1 0 Pc_latch2 (:84)
77 92 F FF + t 0 0 0 4 6 1 0 Pc_latch3 (:83)
49 54 D FF + t 0 0 0 4 7 1 0 Pc_latch4 (:82)
44 49 D FF + t 0 0 0 4 7 1 0 Pc_latch5 (:81)
56 64 D FF + t 0 0 0 4 7 1 0 Pc_latch6 (:80)
55 62 D FF + t 0 0 0 4 7 1 0 Pc_latch7 (:79)
61 70 E FF + t 2 2 0 5 4 9 16 ~PIN002 (:42)
73 86 F FF + t 0 0 0 4 3 17 16 ~PIN004 (:45)
75 89 F FF + t 0 0 0 4 3 9 16 ~PIN006 (:46)
76 91 F FF + t 0 0 0 4 3 9 16 ~PIN008 (:43)
65 76 E OUTPUT t 0 0 0 2 0 0 0 ~PIN010
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\a8255\c8255.rpt
c8255
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 93 F LCELL s t 5 4 1 6 6 0 1 d0~1
- 90 F LCELL s t 4 4 0 4 6 1 0 d0~2
(64) 75 E LCELL s t 5 4 1 6 6 0 1 d1~1
(68) 80 E LCELL s t 4 4 0 4 6 1 0 d1~2
- 42 C LCELL s t 5 4 1 6 6 0 1 d2~1
(10) 9 A LCELL s t 4 4 0 4 6 1 0 d2~2
- 30 B LCELL s t 5 4 1 6 6 0 1 d3~1
(21) 27 B LCELL s t 4 4 0 4 6 1 0 d3~2
- 26 B LCELL s t 5 4 1 6 6 0 1 d4~1
(17) 32 B LCELL s t 4 4 0 4 6 1 0 d4~2
- 36 C LCELL s t 5 4 1 6 6 0 1 d5~1
(31) 45 C LCELL s t 4 4 0 4 6 1 0 d5~2
- 7 A LCELL s t 5 4 1 6 6 0 1 d6~1
(14) 4 A LCELL s t 4 4 0 4 6 1 0 d6~2
(12) 6 A LCELL s t 5 4 1 6 6 0 1 d7~1
- 78 E LCELL s t 4 4 0 4 6 1 0 d7~2
- 79 E TFFE + t 0 0 0 4 3 9 16 ctrreg7 (:39)
- 50 D TFFE + t 0 0 0 4 3 1 1 Pb_latch7 (:71)
- 55 D TFFE + t 0 0 0 4 3 1 1 Pb_latch6 (:72)
(29) 48 C TFFE + t 0 0 0 4 3 1 1 Pb_latch5 (:73)
- 60 D TFFE + t 0 0 0 4 3 1 1 Pb_latch4 (:74)
- 85 F TFFE + t 0 0 0 4 3 1 1 Pb_latch3 (:75)
(52) 59 D TFFE + t 0 0 0 4 3 1 1 Pb_latch2 (:76)
(67) 77 E TFFE + t 0 0 0 4 3 1 1 Pb_latch1 (:77)
- 95 F TFFE + t 0 0 0 4 3 1 1 Pb_latch0 (:78)
- 68 E LCELL s t 1 0 1 2 2 1 4 ~1284~1
- 52 D LCELL s t 1 1 0 2 2 1 3 ~1290~1
(33) 43 C LCELL s t 1 1 0 2 2 1 3 ~1296~1
- 74 E LCELL s t 1 0 1 2 2 3 2 ~1302~1
- 58 D LCELL s t 1 0 1 2 2 9 3 ~1308~1
- 34 C LCELL s t 1 0 1 2 2 8 3 ~1314~1
- 66 E LCELL s t 1 0 1 2 2 9 3 ~1320~1
- 87 F LCELL s t 1 0 1 2 2 2 3 ~1326~1
- 71 E LCELL s t 1 0 1 3 2 19 2 ~1332~1
- 63 D SOFT s t 0 0 0 3 3 1 0 ~1932~1
(4) 16 A SOFT s t 0 0 0 3 3 1 0 ~1947~1
- 47 C SOFT s t 0 0 0 3 3 1 0 ~1962~1
(54) 61 D SOFT s t 0 0 0 3 3 1 0 ~1992~1
- 39 C SOFT s t 0 0 0 3 3 1 0 ~2007~1
(60) 69 E SOFT s t 0 0 0 3 3 1 0 ~2022~1
- 82 F SOFT s t 0 0 0 3 3 1 0 ~2037~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\a8255\c8255.rpt
c8255
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------- LC9 d2~2
| +----------- LC7 d6~1
| | +--------- LC4 d6~2
| | | +------- LC1 d6
| | | | +----- LC6 d7~1
| | | | | +--- LC3 d7
| | | | | | +- LC16 ~1947~1
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'A'
LC | | | | | | | | A B C D E F | Logic cells that feed LAB 'A':
LC7 -> - - * - - - - | * - - - - - | <-- d6~1
LC4 -> - - - * - - - | * - - - - - | <-- d6~2
LC1 -> - * * * - - - | * - - * - - | <-- d6
LC3 -> - - - - * * - | * - - - * - | <-- d7
Pin
1 -> * * * * * * * | * * * * * * | <-- a0
12 -> * * * * * * * | * * * * * * | <-- a1
11 -> * * * * * * * | * * * * * * | <-- cs
34 -> - * - * - - - | * - - - - - | <-- Pa6
52 -> - - - - * * - | * - - - - - | <-- Pa7
5 -> - * - * - - - | * - - - - - | <-- Pch2
17 -> - - - - * * - | * - - - - - | <-- Pch3
84 -> - - - - - - - | - - - - - - | <-- ~PIN003
2 -> - - - - - - - | - - - - - - | <-- ~PIN009
10 -> * * * * * * - | * * * - * * | <-- rd
83 -> - - - - - - - | - - * * * * | <-- wr
LC42 -> * - - - - - - | * - - - - - | <-- d2~1
LC33 -> * - - - - - - | * - * - - - | <-- d2
LC78 -> - - - - - * - | * - - - - - | <-- d7~2
LC46 -> - - - - - - * | * - * - - - | <-- Pa_latch6
LC51 -> - * - * - - - | * - - - - - | <-- Pb6
LC53 -> - - - - * * - | * - - - - - | <-- Pb7
LC70 -> * * * * * * - | * * * - * * | <-- ~PIN002
LC86 -> * * * * * * - | * * * * * * | <-- ~PIN004
LC89 -> * * * * * * - | * * * - * * | <-- ~PIN006
LC91 -> * * * * * * - | * * * - * * | <-- ~PIN008
LC79 -> - - - - - - * | * - * * * * | <-- ctrreg7
LC52 -> - - - - - - * | * - - * - - | <-- ~1290~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\a8255\c8255.rpt
c8255
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------- LC30 d3~1
| +--------------- LC27 d3~2
| | +------------- LC17 d3
| | | +----------- LC26 d4~1
| | | | +--------- LC32 d4~2
| | | | | +------- LC19 d4
| | | | | | +----- LC21 Pb0
| | | | | | | +--- LC24 Pb2
| | | | | | | | +- LC25 Pb4
| | | | | | | | |
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