📄 c8255.rpt
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Project Information d:\a8255\c8255.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 05/03/2008 10:34:24
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
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under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
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net list, support information, device programming or simulation file, or
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***** Project compilation was successful
C8255
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
c8255 EPM7096LC84-7 24 21 16 78 47 81 %
c82551 EPM7032LC44-6 16 0 12 12 0 37 %
c82552 EPM7032LC44-6 6 0 4 4 0 12 %
TOTAL: 46 21 32 94 47 58 %
User Pins: 6 0 32
Project Information d:\a8255\c8255.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Line 76: File d:\a8255\c8255.vhd: Found multiple assignments to the same signal or signal bit "Pc_latch7" in a Process Statement -- only the last assignment will take effect
Warning: Line 76: File d:\a8255\c8255.vhd: Found multiple assignments to the same signal or signal bit "Pc_latch6" in a Process Statement -- only the last assignment will take effect
Warning: Line 76: File d:\a8255\c8255.vhd: Found multiple assignments to the same signal or signal bit "Pc_latch5" in a Process Statement -- only the last assignment will take effect
Warning: Line 76: File d:\a8255\c8255.vhd: Found multiple assignments to the same signal or signal bit "Pc_latch4" in a Process Statement -- only the last assignment will take effect
Warning: Line 76: File d:\a8255\c8255.vhd: Found multiple assignments to the same signal or signal bit "Pc_latch3" in a Process Statement -- only the last assignment will take effect
Warning: Line 76: File d:\a8255\c8255.vhd: Found multiple assignments to the same signal or signal bit "Pc_latch2" in a Process Statement -- only the last assignment will take effect
Warning: Line 76: File d:\a8255\c8255.vhd: Found multiple assignments to the same signal or signal bit "Pc_latch1" in a Process Statement -- only the last assignment will take effect
Warning: Line 76: File d:\a8255\c8255.vhd: Found multiple assignments to the same signal or signal bit "Pc_latch0" in a Process Statement -- only the last assignment will take effect
Warning: GLOBAL primitive on node 'wr' feeds logic -- non-global signal usage may result
Info: Trying to find new partition/fit after discarding assignments as requested with the Partitioner/Fitter Status dialog box
Project Information d:\a8255\c8255.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'wr' chosen for auto global Clock
Project Information d:\a8255\c8255.rpt
** MULTIPLE PIN CONNECTIONS **
For node name 'Pa7'
Connect: {c82551@39, c8255@52}
For node name 'Pa6'
Connect: {c82551@28, c8255@34}
For node name 'Pa5'
Connect: {c82551@41, c8255@24}
For node name 'Pa4'
Connect: {c82551@40, c8255@8}
For node name 'Pa3'
Connect: {c82551@38, c8255@29}
For node name 'Pa2'
Connect: {c82551@37, c8255@33}
For node name 'Pa1'
Connect: {c82551@36, c8255@18}
For node name 'Pa0'
Connect: {c82551@34, c8255@20}
For node name 'Pcl3'
Connect: {c82551@29, c8255@21}
For node name 'Pcl2'
Connect: {c82551@31, c8255@31}
For node name 'Pcl1'
Connect: {c82551@32, c8255@54}
For node name 'Pcl0'
Connect: {c82551@33, c8255@4}
For node name 'Pch3'
Connect: {c82552@38, c8255@17}
For node name 'Pch2'
Connect: {c82552@39, c8255@5}
For node name 'Pch1'
Connect: {c82552@40, c8255@64}
For node name 'Pch0'
Connect: {c82552@41, c8255@60}
For node name '~3819~1' (Same as node '~PIN001')
Connect: {c8255@61, c82551@44, c82551@16}
For node name 'Pa_latch7'
Connect: {c8255@51, c82551@17}
For node name 'Pa_latch6'
Connect: {c8255@30, c82551@14}
For node name 'Pa_latch5'
Connect: {c8255@37, c82551@13}
For node name 'Pa_latch4'
Connect: {c8255@63, c82551@7}
For node name 'Pa_latch3'
Connect: {c8255@50, c82551@6}
For node name 'Pa_latch2'
Connect: {c8255@36, c82551@5}
For node name 'Pa_latch1'
Connect: {c8255@62, c82551@4}
For node name 'Pa_latch0'
Connect: {c8255@80, c82551@20}
For node name '~3997~1' (Same as node '~PIN003')
Connect: {c8255@73, c8255@84}
For node name '~4159~1' (Same as node '~PIN005')
Connect: {c8255@75, c82551@2, c82551@43}
For node name 'Pc_latch3'
Connect: {c8255@77, c82551@8}
For node name 'Pc_latch2'
Connect: {c8255@81, c82551@9}
For node name 'Pc_latch1'
Connect: {c8255@74, c82551@11}
For node name 'Pc_latch0'
Connect: {c8255@71, c82551@12}
For node name '~4277~1' (Same as node '~PIN007')
Connect: {c8255@76, c82552@44, c82552@4}
For node name 'Pc_latch7'
Connect: {c8255@55, c82552@5}
For node name 'Pc_latch6'
Connect: {c8255@56, c82552@6}
For node name 'Pc_latch5'
Connect: {c8255@44, c82552@7}
For node name 'Pc_latch4'
Connect: {c8255@49, c82552@8}
For node name '~906~2' (Same as node '~PIN009')
For node name '~906~1' (Same as node '~PIN010')
Connect: {c8255@2, c8255@65}
Device-Specific Information: d:\a8255\c8255.rpt
c8255
***** Logic for device 'c8255' compiled without errors.
Device: EPM7096LC84-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
Device-Specific Information: d:\a8255\c8255.rpt
c8255
** ERROR SUMMARY **
Info: Chip 'c8255' in device 'EPM7096LC84-7' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
P P P
c a c
~ ~ _ _ _ ~ ~
V P P l l l P P
r C I I a a V a I I
e N P P C N N t t N C t N N
s P G . c c I 0 0 G c c . C c 0 0
c r e a N C h l N 0 a 0 w N h h C I h 0 0
s d t 4 D . 2 0 T 9 0 3 r D 2 0 . O 3 8 6
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
a1 | 12 74 | Pc_latch1
VCCIO | 13 73 | ~PIN004
RESERVED | 14 72 | GND
d7 | 15 71 | Pc_latch0
d6 | 16 70 | d0
Pch3 | 17 69 | Pb3
Pa1 | 18 68 | RESERVED
GND | 19 67 | RESERVED
Pa0 | 20 66 | VCCIO
Pcl3 | 21 65 | ~PIN010
Pb4 | 22 EPM7096LC84-7 64 | Pch1
Pb2 | 23 63 | Pa_latch4
Pa5 | 24 62 | Pa_latch1
Pb0 | 25 61 | ~PIN002
VCCIO | 26 60 | Pch0
d4 | 27 59 | GND
d3 | 28 58 | Pb1
Pa3 | 29 57 | d1
Pa_latch6 | 30 56 | Pc_latch6
Pcl2 | 31 55 | Pc_latch7
GND | 32 54 | Pcl1
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
P P d P P V N P d G V P P N G P P P P P V
a a 5 a a C . b 2 N C c b . N b c a a a C
2 6 _ _ C C 5 D C _ 6 C D 7 _ _ _ 7 C
l l I . I l . l l l I
a a O N a a a a O
t t T t t t t
c c c c c c
h h h h h h
2 5 5 4 3 7
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\a8255\c8255.rpt
c8255
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 7/16( 43%) 9/10( 90%) 16/16(100%) 24/36( 66%)
B: LC17 - LC32 9/16( 56%) 10/10(100%) 12/16( 75%) 23/36( 63%)
C: LC33 - LC48 14/16( 87%) 10/10(100%) 15/16( 93%) 32/36( 88%)
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