📄 a8255.rpt
字号:
LC87 -> - - - - - * - - - - * - - * * * | - - - - - * | <-- ~1326~1
LC82 -> - - - * - - - - - - - - - - - - | - - - - - * | <-- ~2037~1
Pin
1 -> * * * * - * * * * * * * * * - * | * * * * * * | <-- a0
12 -> * * * * - * * * * * * * * * - * | * * * * * * | <-- a1
11 -> * * * * - * * * * * * * * * * * | * * * * * * | <-- cs
20 -> * - * - - - - - - - - - - - - - | - - - - - * | <-- Pa0
4 -> * - * - - - - - - - - - - - - - | - - - - - * | <-- Pcl0
84 -> - - - - - - - - - - - - - - - - | - - - - - - | <-- ~PIN003
2 -> - - - - - - - - - - - - - - - - | - - - - - - | <-- ~PIN009
10 -> * * * - - - - - - - - - - - - - | * * * - * * | <-- rd
9 -> - - - * - * * * * * * * * * - - | - - * * * * | <-- reset
83 -> - - - - - - - - - - - - - - * - | - - * * * * | <-- wr
LC21 -> * - * - - - - - - - - - - - - - | - - - - - * | <-- Pb0
LC70 -> * * * - - - - - - - - - - - - - | * * * - * * | <-- ~PIN002
LC79 -> - - - - - * * * * - - - * * - * | * - * * * * | <-- ctrreg7
LC58 -> - - - - - * * * * - - * * - - - | - - - * - * | <-- ~1308~1
LC34 -> - - - - - * * * * - - - - - - - | - - * * - * | <-- ~1314~1
LC66 -> - - - - - * * * * * - - - - - - | - - - * * * | <-- ~1320~1
LC71 -> - - - * - * * * * * * * - - - - | - - * * * * | <-- ~1332~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\a8255\a8255.rpt
a8255
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
cs : INPUT;
Pa0 : INPUT;
Pa1 : INPUT;
Pa2 : INPUT;
Pa3 : INPUT;
Pa4 : INPUT;
Pa5 : INPUT;
Pa6 : INPUT;
Pa7 : INPUT;
Pch0 : INPUT;
Pch1 : INPUT;
Pch2 : INPUT;
Pch3 : INPUT;
Pcl0 : INPUT;
Pcl1 : INPUT;
Pcl2 : INPUT;
Pcl3 : INPUT;
rd : INPUT;
reset : INPUT;
wr : INPUT;
~PIN003 : INPUT;
~PIN009 : INPUT;
-- Node name is ':39' = 'ctrreg7'
-- Equation name is 'ctrreg7', location is LC079, type is buried.
ctrreg7 = TFFE( _EQ001, GLOBAL( wr), VCC, !reset, VCC);
_EQ001 = a0 & a1 & !cs & !ctrreg7 & _LC068 & _LC071
# a0 & a1 & !cs & ctrreg7 & !_LC068 & _LC071;
-- Node name is 'd0~1'
-- Equation name is 'd0~1', location is LC093, type is buried.
-- synthesized logic cell
_LC093 = LCELL( _EQ002 $ GND);
_EQ002 = !a0 & !cs & !Pa0 & !Pcl0 & ~PIN002 & ~PIN006 & !~PIN008 & !rd &
_X001 & _X002 & _X003 & _X004
# !a0 & !cs & !d0 & !Pcl0 & !~PIN002 & ~PIN006 & !~PIN008 & !rd &
_X001 & _X002 & _X003 & _X004
# !a1 & !cs & !Pa0 & !Pb0 & ~PIN002 & ~PIN004 & !rd & _X001 &
_X002 & _X003 & _X004
# !a1 & !cs & !d0 & !Pb0 & !~PIN002 & ~PIN004 & !rd & _X001 &
_X002 & _X003 & _X004
# !a0 & !a1 & !cs & !d0 & !Pa0 & !rd & _X001 & _X002 & _X003 &
_X004;
_X001 = EXP( a0 & a1 & !d0);
_X002 = EXP( a1 & !d0 & ~PIN008);
_X003 = EXP( a0 & !d0 & !~PIN004);
_X004 = EXP( a1 & !d0 & !~PIN006);
-- Node name is 'd0~2'
-- Equation name is 'd0~2', location is LC090, type is buried.
-- synthesized logic cell
_LC090 = LCELL( _EQ003 $ GND);
_EQ003 = !a0 & !a1 & !cs & !d0 & !~PIN002 & !rd & _X001 & _X002 & _X003 &
_X004
# _LC093;
_X001 = EXP( a0 & a1 & !d0);
_X002 = EXP( a1 & !d0 & ~PIN008);
_X003 = EXP( a0 & !d0 & !~PIN004);
_X004 = EXP( a1 & !d0 & !~PIN006);
-- Node name is 'd0'
-- Equation name is 'd0', location is LC083, type is bidir.
d0 = TRI(_LC083, GLOBAL(!~PIN009));
_LC083 = LCELL( _EQ004 $ _EQ005);
_EQ004 = !a0 & a1 & !cs & !Pcl0 & ~PIN006 & !~PIN008 & !rd & _X001 &
_X002 & _X003 & _X004
# a0 & !a1 & !cs & !Pb0 & ~PIN004 & !rd & _X001 & _X002 & _X003 &
_X004
# !a0 & !a1 & !cs & !Pa0 & ~PIN002 & !rd & _X001 & _X002 & _X003 &
_X004
# _LC090;
_X001 = EXP( a0 & a1 & !d0);
_X002 = EXP( a1 & !d0 & ~PIN008);
_X003 = EXP( a0 & !d0 & !~PIN004);
_X004 = EXP( a1 & !d0 & !~PIN006);
_EQ005 = !cs & !rd & _X001 & _X002 & _X003 & _X004;
_X001 = EXP( a0 & a1 & !d0);
_X002 = EXP( a1 & !d0 & ~PIN008);
_X003 = EXP( a0 & !d0 & !~PIN004);
_X004 = EXP( a1 & !d0 & !~PIN006);
-- Node name is 'd1~1'
-- Equation name is 'd1~1', location is LC075, type is buried.
-- synthesized logic cell
_LC075 = LCELL( _EQ006 $ GND);
_EQ006 = !a0 & !cs & !Pa1 & !Pcl1 & ~PIN002 & ~PIN006 & !~PIN008 & !rd &
_X005 & _X006 & _X007 & _X008
# !a0 & !cs & !d1 & !Pcl1 & !~PIN002 & ~PIN006 & !~PIN008 & !rd &
_X005 & _X006 & _X007 & _X008
# !a1 & !cs & !Pa1 & !Pb1 & ~PIN002 & ~PIN004 & !rd & _X005 &
_X006 & _X007 & _X008
# !a1 & !cs & !d1 & !Pb1 & !~PIN002 & ~PIN004 & !rd & _X005 &
_X006 & _X007 & _X008
# !a0 & !a1 & !cs & !d1 & !Pa1 & !rd & _X005 & _X006 & _X007 &
_X008;
_X005 = EXP( a0 & a1 & !d1);
_X006 = EXP( a1 & !d1 & ~PIN008);
_X007 = EXP( a0 & !d1 & !~PIN004);
_X008 = EXP( a1 & !d1 & !~PIN006);
-- Node name is 'd1~2'
-- Equation name is 'd1~2', location is LC080, type is buried.
-- synthesized logic cell
_LC080 = LCELL( _EQ007 $ GND);
_EQ007 = !a0 & !a1 & !cs & !d1 & !~PIN002 & !rd & _X005 & _X006 & _X007 &
_X008
# _LC075;
_X005 = EXP( a0 & a1 & !d1);
_X006 = EXP( a1 & !d1 & ~PIN008);
_X007 = EXP( a0 & !d1 & !~PIN004);
_X008 = EXP( a1 & !d1 & !~PIN006);
-- Node name is 'd1'
-- Equation name is 'd1', location is LC065, type is bidir.
d1 = TRI(_LC065, GLOBAL(!~PIN009));
_LC065 = LCELL( _EQ008 $ _EQ009);
_EQ008 = !a0 & a1 & !cs & !Pcl1 & ~PIN006 & !~PIN008 & !rd & _X005 &
_X006 & _X007 & _X008
# a0 & !a1 & !cs & !Pb1 & ~PIN004 & !rd & _X005 & _X006 & _X007 &
_X008
# !a0 & !a1 & !cs & !Pa1 & ~PIN002 & !rd & _X005 & _X006 & _X007 &
_X008
# _LC080;
_X005 = EXP( a0 & a1 & !d1);
_X006 = EXP( a1 & !d1 & ~PIN008);
_X007 = EXP( a0 & !d1 & !~PIN004);
_X008 = EXP( a1 & !d1 & !~PIN006);
_EQ009 = !cs & !rd & _X005 & _X006 & _X007 & _X008;
_X005 = EXP( a0 & a1 & !d1);
_X006 = EXP( a1 & !d1 & ~PIN008);
_X007 = EXP( a0 & !d1 & !~PIN004);
_X008 = EXP( a1 & !d1 & !~PIN006);
-- Node name is 'd2~1'
-- Equation name is 'd2~1', location is LC042, type is buried.
-- synthesized logic cell
_LC042 = LCELL( _EQ010 $ GND);
_EQ010 = !a0 & !cs & !Pa2 & !Pcl2 & ~PIN002 & ~PIN006 & !~PIN008 & !rd &
_X009 & _X010 & _X011 & _X012
# !a0 & !cs & !d2 & !Pcl2 & !~PIN002 & ~PIN006 & !~PIN008 & !rd &
_X009 & _X010 & _X011 & _X012
# !a1 & !cs & !Pa2 & !Pb2 & ~PIN002 & ~PIN004 & !rd & _X009 &
_X010 & _X011 & _X012
# !a1 & !cs & !d2 & !Pb2 & !~PIN002 & ~PIN004 & !rd & _X009 &
_X010 & _X011 & _X012
# !a0 & !a1 & !cs & !d2 & !Pa2 & !rd & _X009 & _X010 & _X011 &
_X012;
_X009 = EXP( a0 & a1 & !d2);
_X010 = EXP( a1 & !d2 & ~PIN008);
_X011 = EXP( a0 & !d2 & !~PIN004);
_X012 = EXP( a1 & !d2 & !~PIN006);
-- Node name is 'd2~2'
-- Equation name is 'd2~2', location is LC009, type is buried.
-- synthesized logic cell
_LC009 = LCELL( _EQ011 $ GND);
_EQ011 = !a0 & !a1 & !cs & !d2 & !~PIN002 & !rd & _X009 & _X010 & _X011 &
_X012
# _LC042;
_X009 = EXP( a0 & a1 & !d2);
_X010 = EXP( a1 & !d2 & ~PIN008);
_X011 = EXP( a0 & !d2 & !~PIN004);
_X012 = EXP( a1 & !d2 & !~PIN006);
-- Node name is 'd2'
-- Equation name is 'd2', location is LC033, type is bidir.
d2 = TRI(_LC033, GLOBAL(!~PIN009));
_LC033 = LCELL( _EQ012 $ _EQ013);
_EQ012 = !a0 & a1 & !cs & !Pcl2 & ~PIN006 & !~PIN008 & !rd & _X009 &
_X010 & _X011 & _X012
# a0 & !a1 & !cs & !Pb2 & ~PIN004 & !rd & _X009 & _X010 & _X011 &
_X012
# !a0 & !a1 & !cs & !Pa2 & ~PIN002 & !rd & _X009 & _X010 & _X011 &
_X012
# _LC009;
_X009 = EXP( a0 & a1 & !d2);
_X010 = EXP( a1 & !d2 & ~PIN008);
_X011 = EXP( a0 & !d2 & !~PIN004);
_X012 = EXP( a1 & !d2 & !~PIN006);
_EQ013 = !cs & !rd & _X009 & _X010 & _X011 & _X012;
_X009 = EXP( a0 & a1 & !d2);
_X010 = EXP( a1 & !d2 & ~PIN008);
_X011 = EXP( a0 & !d2 & !~PIN004);
_X012 = EXP( a1 & !d2 & !~PIN006);
-- Node name is 'd3~1'
-- Equation name is 'd3~1', location is LC030, type is buried.
-- synthesized logic cell
_LC030 = LCELL( _EQ014 $ GND);
_EQ014 = !a0 & !cs & !Pa3 & !Pcl3 & ~PIN002 & ~PIN006 & !~PIN008 & !rd &
_X013 & _X014 & _X015 & _X016
# !a0 & !cs & !d3 & !Pcl3 & !~PIN002 & ~PIN006 & !~PIN008 & !rd &
_X013 & _X014 & _X015 & _X016
# !a1 & !cs & !Pa3 & !Pb3 & ~PIN002 & ~PIN004 & !rd & _X013 &
_X014 & _X015 & _X016
# !a1 & !cs & !d3 & !Pb3 & !~PIN002 & ~PIN004 & !rd & _X013 &
_X014 & _X015 & _X016
# !a0 & !a1 & !cs & !d3 & !Pa3 & !rd & _X013 & _X014 & _X015 &
_X016;
_X013 = EXP( a0 & a1 & !d3);
_X014 = EXP( a1 & !d3 & ~PIN008);
_X015 = EXP( a0 & !d3 & !~PIN004);
_X016 = EXP( a1 & !d3 & !~PIN006);
-- Node name is 'd3~2'
-- Equation name is 'd3~2', location is LC027, type is buried.
-- synthesized logic cell
_LC027 = LCELL( _EQ015 $ GND);
_EQ015 = !a0 & !a1 & !cs & !d3 & !~PIN002 & !rd & _X013 & _X014 & _X015 &
_X016
# _LC030;
_X013 = EXP( a0 & a1 & !d3);
_X014 = EXP( a1 & !d3 & ~PIN008);
_X015 = EXP( a0 & !d3 & !~PIN004);
_X016 = EXP( a1 & !d3 & !~PIN006);
-- Node name is 'd3'
-- Equation name is 'd3', location is LC017, type is bidir.
d3 = TRI(_LC017, GLOBAL(!~PIN009));
_LC017 = LCELL( _EQ016 $ _EQ017);
_EQ016 = !a0 & a1 & !cs & !Pcl3 & ~PIN006 & !~PIN008 & !rd & _X013 &
_X014 & _X015 & _X016
# a0 & !a1 & !cs & !Pb3 & ~PIN004 & !rd & _X013 & _X014 & _X015 &
_X016
# !a0 & !a1 & !cs & !Pa3 & ~PIN002 & !rd & _X013 & _X014 & _X015 &
_X016
# _LC027;
_X013 = EXP( a0 & a1 & !d3);
_X014 = EXP( a1 & !d3 & ~PIN008);
_X015 = EXP( a0 & !d3 & !~PIN004);
_X016 = EXP( a1 & !d3 & !~PIN006);
_EQ017 = !cs & !rd & _X013 & _X014 & _X015 & _X016;
_X013 = EXP( a0 & a1 & !d3);
_X014 = EXP( a1 & !d3 & ~PIN008);
_X015 = EXP( a0 & !d3 & !~PIN004);
_X016 = EXP( a1 & !d3 & !~PIN006);
-- Node name is 'd4~1'
-- Equation name is 'd4~1', location is LC026, type is buried.
-- synthesized logic cell
_LC026 = LCELL( _EQ018 $ GND);
_EQ018 = !a0 & !cs & !Pa4 & !Pch0 & ~PIN002 & !~PIN006 & ~PIN008 & !rd &
_X017 & _X018 & _X019 & _X020
# !a0 & !cs & !d4 & !Pch0 & !~PIN002 & !~PIN006 & ~PIN008 & !rd &
_X017 & _X018 & _X019 & _X020
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