📄 a8255.rpt
字号:
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | A B C D E F | Logic cells that feed LAB 'B':
LC30 -> - * - - - - - - - | - * - - - - | <-- d3~1
LC27 -> - - * - - - - - - | - * - - - - | <-- d3~2
LC17 -> * * * - - - - - - | - * - * - - | <-- d3
LC26 -> - - - - * - - - - | - * - - - - | <-- d4~1
LC32 -> - - - - - * - - - | - * - - - - | <-- d4~2
LC19 -> - - - * * * - - - | - * - - * - | <-- d4
LC25 -> - - - * - * - - - | - * - - - - | <-- Pb4
Pin
1 -> * * * * * * - - - | * * * * * * | <-- a0
12 -> * * * * * * - - - | * * * * * * | <-- a1
11 -> * * * * * * - - - | * * * * * * | <-- cs
29 -> * - * - - - - - - | - * - - - - | <-- Pa3
8 -> - - - * - * - - - | - * - - - - | <-- Pa4
60 -> - - - * - * - - - | - * - - - - | <-- Pch0
21 -> * - * - - - - - - | - * - - - - | <-- Pcl3
84 -> - - - - - - - - - | - - - - - - | <-- ~PIN003
2 -> - - - - - - - - - | - - - - - - | <-- ~PIN009
10 -> * * * * * * - - - | * * * - * * | <-- rd
83 -> - - - - - - - - - | - - * * * * | <-- wr
LC81 -> * - * - - - - - - | - * - - - - | <-- Pb3
LC70 -> * * * * * * - - - | * * * - * * | <-- ~PIN002
LC86 -> * * * * * * * * * | * * * * * * | <-- ~PIN004
LC89 -> * * * * * * - - - | * * * - * * | <-- ~PIN006
LC91 -> * * * * * * - - - | * * * - * * | <-- ~PIN008
LC60 -> - - - - - - - - * | - * - * - - | <-- Pb_latch4
LC59 -> - - - - - - - * - | - * - * - - | <-- Pb_latch2
LC95 -> - - - - - - * - - | - * - - - * | <-- Pb_latch0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\a8255\a8255.rpt
a8255
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+--------------------------- LC42 d2~1
| +------------------------- LC33 d2
| | +----------------------- LC36 d5~1
| | | +--------------------- LC45 d5~2
| | | | +------------------- LC40 d5
| | | | | +----------------- LC38 Pa_latch2
| | | | | | +--------------- LC37 Pa_latch5
| | | | | | | +------------- LC46 Pa_latch6
| | | | | | | | +----------- LC35 Pb5
| | | | | | | | | +--------- LC48 Pb_latch5
| | | | | | | | | | +------- LC43 ~1296~1
| | | | | | | | | | | +----- LC34 ~1314~1
| | | | | | | | | | | | +--- LC47 ~1962~1
| | | | | | | | | | | | | +- LC39 ~2007~1
| | | | | | | | | | | | | |
| | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | A B C D E F | Logic cells that feed LAB 'C':
LC33 -> * * - - - - - - - - - * - - | * - * - - - | <-- d2
LC36 -> - - - * - - - - - - - - - - | - - * - - - | <-- d5~1
LC45 -> - - - - * - - - - - - - - - | - - * - - - | <-- d5~2
LC40 -> - - * * * - - - - - * - - - | - - * - - - | <-- d5
LC38 -> - - - - - * - - - - - - - * | - - * - - - | <-- Pa_latch2
LC37 -> - - - - - - * - - - - - * - | - - * - - - | <-- Pa_latch5
LC46 -> - - - - - - - * - - - - - - | * - * - - - | <-- Pa_latch6
LC35 -> - - * - * - - - - - - - - - | - - * - - - | <-- Pb5
LC48 -> - - - - - - - - * * - - - - | - - * - - - | <-- Pb_latch5
LC43 -> - - - - - - - - - * * - * - | - - * * - - | <-- ~1296~1
LC34 -> - - - - - - - - - - - * - * | - - * * - * | <-- ~1314~1
LC47 -> - - - - - - * - - - - - - - | - - * - - - | <-- ~1962~1
LC39 -> - - - - - * - - - - - - - - | - - * - - - | <-- ~2007~1
Pin
1 -> * * * * * * * * - * - - * * | * * * * * * | <-- a0
12 -> * * * * * * * * - * - - * * | * * * * * * | <-- a1
11 -> * * * * * * * * - * * * * * | * * * * * * | <-- cs
33 -> * * - - - - - - - - - - - - | - - * - - - | <-- Pa2
24 -> - - * - * - - - - - - - - - | - - * - - - | <-- Pa5
64 -> - - * - * - - - - - - - - - | - - * - - - | <-- Pch1
31 -> * * - - - - - - - - - - - - | - - * - - - | <-- Pcl2
84 -> - - - - - - - - - - - - - - | - - - - - - | <-- ~PIN003
2 -> - - - - - - - - - - - - - - | - - - - - - | <-- ~PIN009
10 -> * * * * * - - - - - - - - - | * * * - * * | <-- rd
9 -> - - - - - * * * - * - - - - | - - * * * * | <-- reset
83 -> - - - - - - - - - - * * - - | - - * * * * | <-- wr
LC9 -> - * - - - - - - - - - - - - | - - * - - - | <-- d2~2
LC24 -> * * - - - - - - - - - - - - | - - * - - - | <-- Pb2
LC70 -> * * * * * - - - - - - - - - | * * * - * * | <-- ~PIN002
LC86 -> * * * * * - - - * - - - - - | * * * * * * | <-- ~PIN004
LC89 -> * * * * * - - - - - - - - - | * * * - * * | <-- ~PIN006
LC91 -> * * * * * - - - - - - - - - | * * * - * * | <-- ~PIN008
LC79 -> - - - - - - - - - * - - * * | * - * * * * | <-- ctrreg7
LC71 -> - - - - - * * * - - - - - - | - - * * * * | <-- ~1332~1
LC16 -> - - - - - - - * - - - - - - | - - * - - - | <-- ~1947~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\a8255\a8255.rpt
a8255
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC56 Pa_latch3
| +----------------------------- LC57 Pa_latch7
| | +--------------------------- LC51 Pb6
| | | +------------------------- LC53 Pb7
| | | | +----------------------- LC54 Pc_latch4
| | | | | +--------------------- LC49 Pc_latch5
| | | | | | +------------------- LC64 Pc_latch6
| | | | | | | +----------------- LC62 Pc_latch7
| | | | | | | | +--------------- LC50 Pb_latch7
| | | | | | | | | +------------- LC55 Pb_latch6
| | | | | | | | | | +----------- LC60 Pb_latch4
| | | | | | | | | | | +--------- LC59 Pb_latch2
| | | | | | | | | | | | +------- LC52 ~1290~1
| | | | | | | | | | | | | +----- LC58 ~1308~1
| | | | | | | | | | | | | | +--- LC63 ~1932~1
| | | | | | | | | | | | | | | +- LC61 ~1992~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D E F | Logic cells that feed LAB 'D':
LC56 -> * - - - - - - - - - - - - - - * | - - - * - - | <-- Pa_latch3
LC57 -> - * - - - - - - - - - - - - * - | - - - * - - | <-- Pa_latch7
LC54 -> - - - - * - - - - - - - - - - - | - - - * - - | <-- Pc_latch4
LC49 -> - - - - - * - - - - - - - - - - | - - - * - - | <-- Pc_latch5
LC64 -> - - - - - - * - - - - - - - - - | - - - * - - | <-- Pc_latch6
LC62 -> - - - - - - - * - - - - - - - - | - - - * - - | <-- Pc_latch7
LC50 -> - - - * - - - - * - - - - - - - | - - - * - - | <-- Pb_latch7
LC55 -> - - * - - - - - - * - - - - - - | - - - * - - | <-- Pb_latch6
LC60 -> - - - - - - - - - - * - - - - - | - * - * - - | <-- Pb_latch4
LC59 -> - - - - - - - - - - - * - - - - | - * - * - - | <-- Pb_latch2
LC52 -> - - - - - - * - - * - - * - - - | * - - * - - | <-- ~1290~1
LC58 -> - - - - * * * * - - - - - * - * | - - - * - * | <-- ~1308~1
LC63 -> - * - - - - - - - - - - - - - - | - - - * - - | <-- ~1932~1
LC61 -> * - - - - - - - - - - - - - - - | - - - * - - | <-- ~1992~1
Pin
1 -> * * - - * * * * * * * * - - * * | * * * * * * | <-- a0
12 -> * * - - * * * * * * * * - - * * | * * * * * * | <-- a1
11 -> * * - - * * * * * * * * * * * * | * * * * * * | <-- cs
84 -> - - - - - - - - - - - - - - - - | - - - - - - | <-- ~PIN003
2 -> - - - - - - - - - - - - - - - - | - - - - - - | <-- ~PIN009
9 -> * * - - * * * * * * * * - - - - | - - * * * * | <-- reset
83 -> - - - - - - - - - - - - * * - - | - - * * * * | <-- wr
LC17 -> - - - - - - - - - - - - - * - - | - * - * - - | <-- d3
LC1 -> - - - - - - - - - - - - * - - - | * - - * - - | <-- d6
LC86 -> - - * * - - - - - - - - - - - - | * * * * * * | <-- ~PIN004
LC79 -> - - - - * * * * * * * * - - * * | * - * * * * | <-- ctrreg7
LC68 -> - - - - - - - * * - - - - - * - | - - - * * - | <-- ~1284~1
LC43 -> - - - - - * - - - - - - - - - - | - - * * - - | <-- ~1296~1
LC74 -> - - - - * - - - - - * - - - - - | - - - * * - | <-- ~1302~1
LC34 -> - - - - * * * * - - - * - - - - | - - * * - * | <-- ~1314~1
LC66 -> - - - - * * * * - - - - - - - - | - - - * * * | <-- ~1320~1
LC71 -> * * - - * * * * - - - - - - - - | - - * * * * | <-- ~1332~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\a8255\a8255.rpt
a8255
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'E':
Logic cells placed in LAB 'E'
+------------------------------- LC75 d1~1
| +----------------------------- LC80 d1~2
| | +--------------------------- LC65 d1
| | | +------------------------- LC78 d7~2
| | | | +----------------------- LC72 Pa_latch1
| | | | | +--------------------- LC73 Pa_latch4
| | | | | | +------------------- LC67 Pb1
| | | | | | | +----------------- LC70 ~PIN002
| | | | | | | | +--------------- LC76 ~PIN010
| | | | | | | | | +------------- LC79 ctrreg7
| | | | | | | | | | +----------- LC77 Pb_latch1
| | | | | | | | | | | +--------- LC68 ~1284~1
| | | | | | | | | | | | +------- LC74 ~1302~1
| | | | | | | | | | | | | +----- LC66 ~1320~1
| | | | | | | | | | | | | | +--- LC71 ~1332~1
| | | | | | | | | | | | | | | +- LC69 ~2022~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'E'
LC | | | | | | | | | | | | | | | | | A B C D E F | Logic cells that feed LAB 'E':
LC75 -> - * - - - - - - - - - - - - - - | - - - - * - | <-- d1~1
LC80 -> - - * - - - - - - - - - - - - - | - - - - * - | <-- d1~2
LC65 -> * * * - - - - - - - - - - * - - | - - - - * - | <-- d1
LC72 -> - - - - * - - - - - - - - - - * | - - - - * - | <-- Pa_latch1
LC73 -> - - - - - * - - - - - - - - - - | - - - - * - | <-- Pa_latch4
LC67 -> * - * - - - - - - - - - - - - - | - - - - * - | <-- Pb1
LC70 -> * * * * - - - * - - - - - - - - | * * * - * * | <-- ~PIN002
LC79 -> - - - - - * - - - * * - - - - * | * - * * * * | <-- ctrreg7
LC77 -> - - - - - - * - - - * - - - - - | - - - - * - | <-- Pb_latch1
LC68 -> - - - - - - - - - * - * - - - - | - - - * * - | <-- ~1284~1
LC74 -> - - - - - * - * - - - - * - - - | - - - * * - | <-- ~1302~1
LC66 -> - - - - - - - - - - * - - * - * | - - - * * * | <-- ~1320~1
LC71 -> - - - - * - - * - * - - - - * - | - - * * * * | <-- ~1332~1
LC69 -> - - - - * - - - - - - - - - - - | - - - - * - | <-- ~2022~1
Pin
1 -> * * * * * * - * - * * - - - - * | * * * * * * | <-- a0
12 -> * * * * * * - * - * * - - - - * | * * * * * * | <-- a1
11 -> * * * * * * - * * * * * * * * * | * * * * * * | <-- cs
18 -> * - * - - - - - - - - - - - - - | - - - - * - | <-- Pa1
54 -> * - * - - - - - - - - - - - - - | - - - - * - | <-- Pcl1
84 -> - - - - - - - - - - - - - - - - | - - - - - - | <-- ~PIN003
2 -> - - - - - - - - - - - - - - - - | - - - - - - | <-- ~PIN009
10 -> * * * * - - - - * - - - - - - - | * * * - * * | <-- rd
9 -> - - - - * * - * - * * - - - * - | - - * * * * | <-- reset
83 -> - - - - - - - * - - - * * * * - | - - * * * * | <-- wr
LC19 -> - - - - - - - * - - - - * - - - | - * - - * - | <-- d4
LC6 -> - - - * - - - - - - - - - - - - | - - - - * - | <-- d7~1
LC3 -> - - - * - - - - - - - * - - * - | * - - - * - | <-- d7
LC86 -> * * * * - - * - - - - - - - - - | * * * * * * | <-- ~PIN004
LC89 -> * * * * - - - - - - - - - - - - | * * * - * * | <-- ~PIN006
LC91 -> * * * * - - - - - - - - - - - - | * * * - * * | <-- ~PIN008
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\a8255\a8255.rpt
a8255
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'F':
Logic cells placed in LAB 'F'
+------------------------------- LC93 d0~1
| +----------------------------- LC90 d0~2
| | +--------------------------- LC83 d0
| | | +------------------------- LC94 Pa_latch0
| | | | +----------------------- LC81 Pb3
| | | | | +--------------------- LC84 Pc_latch0
| | | | | | +------------------- LC88 Pc_latch1
| | | | | | | +----------------- LC96 Pc_latch2
| | | | | | | | +--------------- LC92 Pc_latch3
| | | | | | | | | +------------- LC86 ~PIN004
| | | | | | | | | | +----------- LC89 ~PIN006
| | | | | | | | | | | +--------- LC91 ~PIN008
| | | | | | | | | | | | +------- LC85 Pb_latch3
| | | | | | | | | | | | | +----- LC95 Pb_latch0
| | | | | | | | | | | | | | +--- LC87 ~1326~1
| | | | | | | | | | | | | | | +- LC82 ~2037~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'F'
LC | | | | | | | | | | | | | | | | | A B C D E F | Logic cells that feed LAB 'F':
LC93 -> - * - - - - - - - - - - - - - - | - - - - - * | <-- d0~1
LC90 -> - - * - - - - - - - - - - - - - | - - - - - * | <-- d0~2
LC83 -> * * * - - - - - - - - - - - * - | - - - - - * | <-- d0
LC94 -> - - - * - - - - - - - - - - - * | - - - - - * | <-- Pa_latch0
LC84 -> - - - - - * - - - - - - - - - - | - - - - - * | <-- Pc_latch0
LC88 -> - - - - - - * - - - - - - - - - | - - - - - * | <-- Pc_latch1
LC96 -> - - - - - - - * - - - - - - - - | - - - - - * | <-- Pc_latch2
LC92 -> - - - - - - - - * - - - - - - - | - - - - - * | <-- Pc_latch3
LC86 -> * * * - * - - - - * - - - - - - | * * * * * * | <-- ~PIN004
LC89 -> * * * - - - - - - - * - - - - - | * * * - * * | <-- ~PIN006
LC91 -> * * * - - - - - - - - * - - - - | * * * - * * | <-- ~PIN008
LC85 -> - - - - * - - - - - - - * - - - | - - - - - * | <-- Pb_latch3
LC95 -> - - - - - - - - - - - - - * - - | - * - - - * | <-- Pb_latch0
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