divider.vhd

来自「自己用VHDL写的键盘程序」· VHDL 代码 · 共 29 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity divider is
    port(clk: in std_logic;
         key_clock:out std_logic);
end divider;
architecture one of divider is
    signal div:std_logic_vector(6 downto 0);
    signal count:std_logic_vector(7 downto 0);
    signal a:std_logic;
begin
     process(clk)
     begin
           if clk'event and clk='0' then
               div<=div+1;
               if (div="1001110") then
                   if (count="00100000") then
                      count<="00000000";
                      a<='1';
                   else
                      count<=count+1;
                      a<='0';
                   end if;
                end if;
            end if;
        end process;
     key_clock<=a; 
end one;