geweizd.vhd

来自「自己用VHDL写的键盘程序」· VHDL 代码 · 共 20 行

library ieee;
use ieee.std_logic_1164.all;
entity geweizd is
      port(a:in std_logic;
           b:in std_logic;
           key_down:out std_logic);
end geweizd;
architecture one of geweizd is
     signal c:std_logic;
begin
     process(b)
     begin
         if b='1' then 
             c<=a;
         else
             c<='0';
         end if;
     end process;
     key_down<=c;
end one;