zd4.vhd

来自「自己用VHDL写的键盘程序」· VHDL 代码 · 共 20 行

library ieee;
use ieee.std_logic_1164.all;
entity zd4 is
      port(a:in std_logic_vector(3 downto 0);
           b:in std_logic;
           key_word:out std_logic_vector(3 downto 0));
end zd4;
architecture one of zd4 is
     signal c:std_logic_vector(3 downto 0);
begin
     process(b)
     begin
         if b='1' then 
             c<=a;
         else
             c<="0000";
         end if;
     end process;
     key_word<=c;
end one;