qep.v

来自「一个QEP电路的verilog代码。输入信号是光电编码器的A相和B相信号和一个处」· Verilog 代码 · 共 73 行

module qep( 
  rst,ina,inb,clkin,clkout,dirout						
);

input rst,ina,inb;//复们信号，光电编码器A相和B输入信号
input clkin;//处理时钟输入信号
output clkout,dirout;//输出时钟和方向信号

reg dirout;

reg ina1,ina2;
always @(negedge rst or posedge clkin)begin
	if(!rst)begin
		ina1 <= 1'b0;
		ina2 <= 1'b0;
	end
	else begin
		ina1 <= ina;
		ina2 <= ina1;
	end
end

wire ina_edge = ina1 ^ ina2;

reg inb1,inb2;
always @(negedge rst or posedge clkin)begin
	if(!rst)begin
		inb1 <= 1'b0;
		inb2 <= 1'b0;
	end
	else begin
		inb1 <= inb;
		inb2 <= inb1;
	end
end

wire inb_edge = inb1 ^ inb2;

reg inb_new;
wire ab = ina ^ inb;
always @(negedge rst or negedge ina_edge)begin
	if(!rst)begin
		inb_new <= 1'b0;
		dirout <= 1'b0;
   end
	else begin
		inb_new <= inb;
		dirout <= ab;
	end
end

reg ina_new;
always @(negedge rst or negedge inb_edge)begin
	if(!rst)
		ina_new <= 1'b0;
	else
		ina_new <= ina;
end

wire clk_temp1 = ina_new ^ inb_new;
reg clk_temp2;
always @(negedge rst or posedge clkin)begin
	if(!rst)begin
		clk_temp2 <= 1'b0;
	end
	else begin
		clk_temp2 <= clk_temp1;
	end
end
assign clkout = clk_temp1 ^ clk_temp2;

endmodule