hour.vhd

来自「个人设计的基于VHDL的数字电子日历 在MAX+PLUSH软件平台上编译、仿真」· VHDL 代码 · 共 32 行

LIBRARY ieee; 
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY hour IS
	PORT(
         clk,reset		: IN  STD_LOGIC;
		 daout          : OUT STD_LOGIC_VECTOR(5 downto 0)                 
        );
END hour;

ARCHITECTURE a OF hour IS
 BEGIN
  PROCESS (Clk)
         VARIABLE tmpa         : STD_LOGIC_VECTOR(3 downto 0);
		 VARIABLE tmpb         : STD_LOGIC_VECTOR(1 downto 0);
  BEGIN
	IF reset='0' THEN  tmpb :="00"; tmpa :="0000";
    ELSE    
         IF (CLK'event AND CLK='1') THEN
               IF tmpa="1001" THEN 
                     tmpa:="0000"; tmpb:=tmpb+1;
               ELSIF (tmpb="10" AND tmpa="0011") THEN 
                      tmpb:="00"; tmpa:="0000";
               ELSE  tmpa := tmpa+1;
               END IF; 
            END IF;
        END IF;
	 daout(3 downto 0) <= tmpa; daout(5 downto 4)<= tmpb;   
   END PROCESS ;
END a;