seltime.vhd

来自「个人设计的基于VHDL的数字电子日历 在MAX+PLUSH软件平台上编译、仿真」· VHDL 代码 · 共 50 行

LIBRARY ieee; 
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY seltime IS
	PORT(
         clk,reset  : IN  STD_LOGIC;
         sec,min   :in  std_logic_vector(6 downto 0);
         hour      :in std_logic_vector(5 downto 0);
		 daout          : OUT STD_LOGIC_VECTOR(3 downto 0);
         sel       :out std_logic_vector(2 downto 0)                
        );
END seltime;

ARCHITECTURE a OF seltime IS
 signal sel_b :std_logic_vector(2 downto 0);
 BEGIN
  PROCESS (Clk)
         VARIABLE tmpa         : STD_LOGIC_VECTOR(2 downto 0);
  BEGIN
	IF reset='0' THEN  tmpa:="000";
    ELSE    
         IF (CLK'event AND CLK='1') THEN
               tmpa := tmpa+1;
               END IF; 
            END IF; 
     sel<=tmpa;
     sel_b<=tmpa;
   END PROCESS ;
 process( sel_b)
begin
	CASE sel_b IS
		WHEN "000" =>
		    daout<=sec(3 downto 0);
        WHEN "001" =>
		    daout<='0'&sec(6 downto 4);
        WHEN "010" =>
		    daout<=min(3 downto 0);
        WHEN "011" =>
		    daout<='0'&min(6 downto 4);
        WHEN "100" =>
		    daout<=hour(3 downto 0);
        WHEN "101" =>
		    daout<='0'&'0'&hour(5 downto 4);
		WHEN OTHERS =>
		    daout<="0000";
	END CASE;
	end process;
END a;