serial_count.vhd

个人设计的基于VHDL的数字电子日历 在MAX+PLUSH软件平台上编译、仿真

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY serial_count IS
    PORT (data : IN STD_LOGIC_vector(7 downto 0);                    
         count: out integer range 0 to 8;                     
          error : OUT boolean  );          
   END serial_count;
ARCHITECTURE behav OF serial_count IS
BEGIN
P_REG: PROCESS(data)
variable a,b :boolean;
variable count1 : integer range 0 to 8;
BEGIN
error<=FALSE;
a:=false;
b:=false;
count1:=0;
LY:for i in 0 to 7 loop
if (b and data(i)='0') then
count1:=0;
error<=true;
exit;

elsif( a and data(i)='1' )then
b:=true;
elsif (data(i)='0')then
a:=true;
count1:=count1+1;
end if;
end loop;
count<=count1;
END PROCESS P_REG ;
END  behav;