tb_hy5ps12821bf.vhd

ddr 2 接口读写测试模块 ddr 2 接口读写测试模块

-- TB_HY5PS12821BF.vhd
--

USE     STD.textio.all;
LIBRARY IEEE;
USE     IEEE.STD_LOGIC_1164.all;
USE     IEEE.STD_LOGIC_TEXTIO.all;
USE     WORK.HY5PS12821BF_PACK.all;
-----------------------------------------------------------------------------
entity E is
end E;
-----------------------------------------------------------------------------
Architecture A of E is

   signal      CLK, CLKB, CKE, CSB, RASB, CASB, WEB, DM_RDQS : std_logic;
   signal      ADDR : std_logic_vector(13 downto 0);
   signal      DQ : std_logic_vector(7 downto 0);
   signal      DQS, DQSB, RDQSB : std_logic;
   signal      BA : std_logic_vector(1 downto 0);
   constant    CLK_PERIOD : time := 3 ns;

   component HY5PS12821BF
     generic (
        TimingCheckFlag : boolean       := TRUE;
        PUSCheckFlag    : boolean       := FALSE;
        Part_Number     : PART_NUM_TYPE := B667D);
     port ( CLK     : in    std_logic ;
            CLKB    : in    std_logic ;
            CKE     : in    std_logic ;
            CSB     : in    std_logic ;
            RASB    : in    std_logic ;
            CASB    : in    std_logic ;
            WEB     : in    std_logic ;
            BA      : in    std_logic_vector (1  downto 0) ;
            ADDR    : in    std_logic_vector (13 downto 0) ;
            
            RDQSB   :   out std_logic ;
            DM_RDQS : inout std_logic := 'Z' ;
            DQS     : inout std_logic := 'Z' ;
            DQSB    : inout std_logic := 'Z' ;
            DQ      : inout std_logic_vector (7  downto 0) := (others => 'Z') ) ;
   End component HY5PS12821BF;
 
begin
----------------------------------------------------------
  UUT : HY5PS12821BF
      Generic Map (TRUE, FALSE, B667D)
      Port Map ( CLK, CLKB, CKE, CSB, RASB, CASB, WEB, BA, ADDR, 

                 RDQSB, DM_RDQS, DQS, DQSB, DQ ) ;      
  --------------------------------------------------------
  TB : block

   begin

   STIMULUS : process

    file testvectors : TEXT open read_mode is "test_vec.dat";
    variable L : Line;
    variable CLKv, CKEv, CSBv, RASBv, CASBv, WEBv, LDMv, UDMv : std_logic;
    variable A0v, A1v, A2v, A3v, A4v, A5v, A6v, A7v, A8v, A9v : std_logic;
    variable A10v, A11v, A12v, A13v, BA0v, BA1v, LDQSv, UDQSv, CLKBv : std_logic;
    variable DQ0v, DQ1v, DQ2v, DQ3v, DQ4v, DQ5v, DQ6v, DQ7v : std_logic;
    variable DQ8v, DQ9v, DQ10v, DQ11v, DQ12v, DQ13v, DQ14v, DQ15v : std_logic;
    variable TEMP : Character;

    begin
      loop
        if (ENDFILE (testvectors)) then
          assert false report "Simulation finished." severity failure;exit;
        end if;
        readline (testvectors, L);
        exit when (L=NULL) or (L'length = 0);
        read (L, TEMP);
        loop
          if (TEMP = '0' or TEMP = '1') then
            CLKv := CHAR_TO_STD_LOGIC(TEMP);
            exit;
          else
            readline (testvectors, L);
            exit when (L=NULL) or (L'length = 0);
            read (L, TEMP);
          end if;
        end loop;
        read (L, CKEv);
        read (L, CSBv);
        read (L, RASBv);
        read (L, CASBv);
        read (L, WEBv);
        read (L, UDMv);
        read (L, LDMv);
        read (L, UDQSv);
        read (L, LDQSv);
        read (L, BA1v);
        read (L, BA0v);
        read (L, A13v);
        read (L, A12v);
        read (L, A11v);
        read (L, A10v);
        read (L, A9v);
        read (L, A8v);
        read (L, A7v);
        read (L, A6v);
        read (L, A5v);
        read (L, A4v);
        read (L, A3v);
        read (L, A2v);
        read (L, A1v);
        read (L, A0v);
        read (L, DQ7v);
        read (L, DQ6v);
        read (L, DQ5v);
        read (L, DQ4v);
        read (L, DQ3v);
        read (L, DQ2v);
        read (L, DQ1v);
        read (L, DQ0v);
        CLK <= CLKv;
        CLKB <= not CLKv;
        CKE <= CKEv;
        CSB <= CSBv;
        RASB <= RASBv;
        CASB <= CASBv;
        WEB <= WEBv;
        DM_RDQS <= '0' ; 
        DQS <= LDQSv;
        BA <= BA1v&BA0v;
        ADDR <= A13v&A12v&A11v&A10v&A9v&A8v&A7v&A6v&A5v&A4v&A3v&A2v&A1v&A0v;
        DQ <= transport DQ7v&DQ6v&DQ5v&DQ4v&DQ3v&DQ2v&DQ1v&DQ0v after CLK_PERIOD/4;
        wait for CLK_PERIOD / 2;
        end loop;
    end process STIMULUS;

   end block;
  ------------------------------------------------
end A;