cpu_interface.v

UART的一段VHDL程序

//
// Module UART_V.cpu_interface.intconx
//
// Created:
//          by - user.group (host.domain)
//          at - 10:56:05 30 Aug 2001
//
// Generated by Mentor Graphics' HDL Designer(TM) 2001.5
//

`resetall
`timescale 1ns/10ps
module cpu_interface( 
   clk, 
   clk_div_en, 
   clr_int_en, 
   cs, 
   div_data, 
   nrw, 
   rst, 
   ser_if_data, 
   xmitdt_en, 
   clear_flags, 
   data_out, 
   enable_write, 
   start_xmit
);


// Internal Declarations

input        clk;
input        clk_div_en;
input        clr_int_en;
input        cs;
input  [7:0] div_data;
input        nrw;
input        rst;
input  [7:0] ser_if_data;
input        xmitdt_en;
output       clear_flags;
output [7:0] data_out;
output       enable_write;
output       start_xmit;


wire        clk;
wire        clk_div_en;
wire        clr_int_en;
wire        cs;
wire [7:0]  div_data;
wire        nrw;
wire        rst;
wire [7:0]  ser_if_data;
wire        xmitdt_en;
wire        clear_flags;
wire [7:0]  data_out;
wire        enable_write;
wire        start_xmit;

// Local declarations


   
// Internal signal declarations


// Instances 
control_operation I0( 
   .clk          (clk), 
   .clr_int_en   (clr_int_en), 
   .cs           (cs), 
   .nrw          (nrw), 
   .rst          (rst), 
   .xmitdt_en    (xmitdt_en), 
   .clear_flags  (clear_flags), 
   .enable_write (enable_write), 
   .start_xmit   (start_xmit)
); 

// ModuleWare instances.

// HDL Embedded Text Block 1 data_out_mux
assign data_out = (clk_div_en == 1) ? div_data : ser_if_data;
endmodule // cpu_interface