threeflift.tan.qmsg

电梯控制器的设计与分析---控制器的层数为三层,,电梯到达有停站请求的楼层

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "DOUT1\[0\]\$latch " "Warning: Node \"DOUT1\[0\]\$latch\" is a latch" {  } { { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 211 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DOUT1\[1\]\$latch " "Warning: Node \"DOUT1\[1\]\$latch\" is a latch" {  } { { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 211 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "LIFTCLK " "Info: Assuming node \"LIFTCLK\" is an undefined clock" {  } { { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 8 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "LIFTCLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "BUTTONCLK " "Info: Assuming node \"BUTTONCLK\" is an undefined clock" {  } { { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 7 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "BUTTONCLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "LIFTCLK register POSITION\[0\]~reg0 register MYLIFT.doorclose 104.17 MHz 9.6 ns Internal " "Info: Clock \"LIFTCLK\" has Internal fmax of 104.17 MHz between source register \"POSITION\[0\]~reg0\" and destination register \"MYLIFT.doorclose\" (period= 9.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.500 ns + Longest register register " "Info: + Longest register to register delay is 8.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns POSITION\[0\]~reg0 1 REG LC1_B4 28 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B4; Fanout = 28; REG Node = 'POSITION\[0\]~reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { POSITION[0]~reg0 } "NODE_NAME" } } { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 36 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 1.900 ns FDNLIGHT~117 2 COMB LC3_B4 4 " "Info: 2: + IC(0.300 ns) + CELL(1.600 ns) = 1.900 ns; Loc. = LC3_B4; Fanout = 4; COMB Node = 'FDNLIGHT~117'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { POSITION[0]~reg0 FDNLIGHT~117 } "NODE_NAME" } } { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.600 ns) 4.500 ns MYLIFT~2563 3 COMB LC2_B3 1 " "Info: 3: + IC(1.000 ns) + CELL(1.600 ns) = 4.500 ns; Loc. = LC2_B3; Fanout = 1; COMB Node = 'MYLIFT~2563'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.600 ns" { FDNLIGHT~117 MYLIFT~2563 } "NODE_NAME" } } { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 6.200 ns MYLIFT~2567 4 COMB LC5_B3 1 " "Info: 4: + IC(0.300 ns) + CELL(1.400 ns) = 6.200 ns; Loc. = LC5_B3; Fanout = 1; COMB Node = 'MYLIFT~2567'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { MYLIFT~2563 MYLIFT~2567 } "NODE_NAME" } } { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(1.100 ns) 8.500 ns MYLIFT.doorclose 5 REG LC4_B9 5 " "Info: 5: + IC(1.200 ns) + CELL(1.100 ns) = 8.500 ns; Loc. = LC4_B9; Fanout = 5; REG Node = 'MYLIFT.doorclose'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.300 ns" { MYLIFT~2567 MYLIFT.doorclose } "NODE_NAME" } } { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.700 ns ( 67.06 % ) " "Info: Total cell delay = 5.700 ns ( 67.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns ( 32.94 % ) " "Info: Total interconnect delay = 2.800 ns ( 32.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.500 ns" { POSITION[0]~reg0 FDNLIGHT~117 MYLIFT~2563 MYLIFT~2567 MYLIFT.doorclose } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.500 ns" { POSITION[0]~reg0 FDNLIGHT~117 MYLIFT~2563 MYLIFT~2567 MYLIFT.doorclose } { 0.000ns 0.300ns 1.000ns 0.300ns 1.200ns } { 0.000ns 1.600ns 1.600ns 1.400ns 1.100ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "LIFTCLK destination 2.400 ns + Shortest register " "Info: + Shortest clock path from clock \"LIFTCLK\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns LIFTCLK 1 CLK PIN_126 17 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 17; CLK Node = 'LIFTCLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LIFTCLK } "NODE_NAME" } } { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns MYLIFT.doorclose 2 REG LC4_B9 5 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC4_B9; Fanout = 5; REG Node = 'MYLIFT.doorclose'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { LIFTCLK MYLIFT.doorclose } "NODE_NAME" } } { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { LIFTCLK MYLIFT.doorclose } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { LIFTCLK LIFTCLK~out MYLIFT.doorclose } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "LIFTCLK source 2.400 ns - Longest register " "Info: - Longest clock path from clock \"LIFTCLK\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns LIFTCLK 1 CLK PIN_126 17 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 17; CLK Node = 'LIFTCLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LIFTCLK } "NODE_NAME" } } { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns POSITION\[0\]~reg0 2 REG LC1_B4 28 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_B4; Fanout = 28; REG Node = 'POSITION\[0\]~reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { LIFTCLK POSITION[0]~reg0 } "NODE_NAME" } } { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 36 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { LIFTCLK POSITION[0]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { LIFTCLK LIFTCLK~out POSITION[0]~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { LIFTCLK MYLIFT.doorclose } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { LIFTCLK LIFTCLK~out MYLIFT.doorclose } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { LIFTCLK POSITION[0]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { LIFTCLK LIFTCLK~out POSITION[0]~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 36 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.500 ns" { POSITION[0]~reg0 FDNLIGHT~117 MYLIFT~2563 MYLIFT~2567 MYLIFT.doorclose } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.500 ns" { POSITION[0]~reg0 FDNLIGHT~117 MYLIFT~2563 MYLIFT~2567 MYLIFT.doorclose } { 0.000ns 0.300ns 1.000ns 0.300ns 1.200ns } { 0.000ns 1.600ns 1.600ns 1.400ns 1.100ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { LIFTCLK MYLIFT.doorclose } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { LIFTCLK LIFTCLK~out MYLIFT.doorclose } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { LIFTCLK POSITION[0]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { LIFTCLK LIFTCLK~out POSITION[0]~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "BUTTONCLK register register STOPLIGHT\[2\]~reg0 STOPLIGHT\[2\]~reg0 200.0 MHz Internal " "Info: Clock \"BUTTONCLK\" Internal fmax is restricted to 200.0 MHz between source register \"STOPLIGHT\[2\]~reg0\" and destination register \"STOPLIGHT\[2\]~reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.800 ns + Longest register register " "Info: + Longest register to register delay is 2.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns STOPLIGHT\[2\]~reg0 1 REG LC1_B28 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B28; Fanout = 8; REG Node = 'STOPLIGHT\[2\]~reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { STOPLIGHT[2]~reg0 } "NODE_NAME" } } { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 188 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 1.700 ns STOPLIGHT~280 2 COMB LC6_B28 1 " "Info: 2: + IC(0.300 ns) + CELL(1.400 ns) = 1.700 ns; Loc. = LC6_B28; Fanout = 1; COMB Node = 'STOPLIGHT~280'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { STOPLIGHT[2]~reg0 STOPLIGHT~280 } "NODE_NAME" } } { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.800 ns) 2.800 ns STOPLIGHT\[2\]~reg0 3 REG LC1_B28 8 " "Info: 3: + IC(0.300 ns) + CELL(0.800 ns) = 2.800 ns; Loc. = LC1_B28; Fanout = 8; REG Node = 'STOPLIGHT\[2\]~reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.100 ns" { STOPLIGHT~280 STOPLIGHT[2]~reg0 } "NODE_NAME" } } { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 188 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 78.57 % ) " "Info: Total cell delay = 2.200 ns ( 78.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns ( 21.43 % ) " "Info: Total interconnect delay = 0.600 ns ( 21.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { STOPLIGHT[2]~reg0 STOPLIGHT~280 STOPLIGHT[2]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.800 ns" { STOPLIGHT[2]~reg0 STOPLIGHT~280 STOPLIGHT[2]~reg0 } { 0.000ns 0.300ns 0.300ns } { 0.000ns 1.400ns 0.800ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "BUTTONCLK destination 2.400 ns + Shortest register " "Info: + Shortest clock path from clock \"BUTTONCLK\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns BUTTONCLK 1 CLK PIN_54 7 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 7; CLK Node = 'BUTTONCLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { BUTTONCLK } "NODE_NAME" } } { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns STOPLIGHT\[2\]~reg0 2 REG LC1_B28 8 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_B28; Fanout = 8; REG Node = 'STOPLIGHT\[2\]~reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { BUTTONCLK STOPLIGHT[2]~reg0 } "NODE_NAME" } } { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 188 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { BUTTONCLK STOPLIGHT[2]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { BUTTONCLK BUTTONCLK~out STOPLIGHT[2]~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "BUTTONCLK source 2.400 ns - Longest register " "Info: - Longest clock path from clock \"BUTTONCLK\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns BUTTONCLK 1 CLK PIN_54 7 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 7; CLK Node = 'BUTTONCLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { BUTTONCLK } "NODE_NAME" } } { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns STOPLIGHT\[2\]~reg0 2 REG LC1_B28 8 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_B28; Fanout = 8; REG Node = 'STOPLIGHT\[2\]~reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { BUTTONCLK STOPLIGHT[2]~reg0 } "NODE_NAME" } } { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 188 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { BUTTONCLK STOPLIGHT[2]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { BUTTONCLK BUTTONCLK~out STOPLIGHT[2]~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { BUTTONCLK STOPLIGHT[2]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { BUTTONCLK BUTTONCLK~out STOPLIGHT[2]~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { BUTTONCLK STOPLIGHT[2]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { BUTTONCLK BUTTONCLK~out STOPLIGHT[2]~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 188 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 188 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { STOPLIGHT[2]~reg0 STOPLIGHT~280 STOPLIGHT[2]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.800 ns" { STOPLIGHT[2]~reg0 STOPLIGHT~280 STOPLIGHT[2]~reg0 } { 0.000ns 0.300ns 0.300ns } { 0.000ns 1.400ns 0.800ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { BUTTONCLK STOPLIGHT[2]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { BUTTONCLK BUTTONCLK~out STOPLIGHT[2]~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { BUTTONCLK STOPLIGHT[2]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { BUTTONCLK BUTTONCLK~out STOPLIGHT[2]~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { STOPLIGHT[2]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { STOPLIGHT[2]~reg0 } {  } {  } "" } } { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 188 0 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "POSITION\[0\]~reg0 RESET LIFTCLK 11.200 ns register " "Info: tsu for register \"POSITION\[0\]~reg0\" (data pin = \"RESET\", clock pin = \"LIFTCLK\") is 11.200 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.000 ns + Longest pin register " "Info: + Longest pin to register delay is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns RESET 1 PIN PIN_19 21 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_19; Fanout = 21; PIN Node = 'RESET'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RESET } "NODE_NAME" } } { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.400 ns) + CELL(1.400 ns) 10.700 ns POSITION\[0\]~88 2 COMB LC5_B8 4 " "Info: 2: + IC(4.400 ns) + CELL(1.400 ns) = 10.700 ns; Loc. = LC5_B8; Fanout = 4; COMB Node = 'POSITION\[0\]~88'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.800 ns" { RESET POSITION[0]~88 } "NODE_NAME" } } { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(1.000 ns) 13.000 ns POSITION\[0\]~reg0 3 REG LC1_B4 28 " "Info: 3: + IC(1.300 ns) + CELL(1.000 ns) = 13.000 ns; Loc. = LC1_B4; Fanout = 28; REG Node = 'POSITION\[0\]~reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.300 ns" { POSITION[0]~88 POSITION[0]~reg0 } "NODE_NAME" } } { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 36 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.300 ns ( 56.15 % ) " "Info: Total cell delay = 7.300 ns ( 56.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.700 ns ( 43.85 % ) " "Info: Total interconnect delay = 5.700 ns ( 43.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "13.000 ns" { RESET POSITION[0]~88 POSITION[0]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "13.000 ns" { RESET RESET~out POSITION[0]~88 POSITION[0]~reg0 } { 0.000ns 0.000ns 4.400ns 1.300ns } { 0.000ns 4.900ns 1.400ns 1.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 36 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "LIFTCLK destination 2.400 ns - Shortest register " "Info: - Shortest clock path from clock \"LIFTCLK\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns LIFTCLK 1 CLK PIN_126 17 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 17; CLK Node = 'LIFTCLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LIFTCLK } "NODE_NAME" } } { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns POSITION\[0\]~reg0 2 REG LC1_B4 28 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_B4; Fanout = 28; REG Node = 'POSITION\[0\]~reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { LIFTCLK POSITION[0]~reg0 } "NODE_NAME" } } { "THREEFLIFT.vhd" "" { Text "F:/THREEFLIFT/THREEFLIFT.vhd" 36 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { LIFTCLK POSITION[0]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { LIFTCLK LIFTCLK~out POSITION[0]~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "13.000 ns" { RESET POSITION[0]~88 POSITION[0]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "13.000 ns" { RESET RESET~out POSITION[0]~88 POSITION[0]~reg0 } { 0.000ns 0.000ns 4.400ns 1.300ns } { 0.000ns 4.900ns 1.400ns 1.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { LIFTCLK POSITION[0]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { LIFTCLK LIFTCLK~out POSITION[0]~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}