threeflift.tan.rpt

电梯控制器的设计与分析---控制器的层数为三层,,电梯到达有停站请求的楼层

; N/A           ; None        ; -8.100 ns ; F3DNBUTTON  ; FDNLIGHT[3]~reg0  ; BUTTONCLK ;
; N/A           ; None        ; -8.100 ns ; F1UPBUTTON  ; FUPLIGHT[1]~reg0  ; BUTTONCLK ;
; N/A           ; None        ; -8.300 ns ; RESET       ; DOORLIGHT~reg0    ; LIFTCLK   ;
; N/A           ; None        ; -8.400 ns ; F1UPBUTTON  ; FUPLIGHT[2]~reg0  ; BUTTONCLK ;
; N/A           ; None        ; -9.300 ns ; RESET       ; POSITION[0]~reg0  ; LIFTCLK   ;
; N/A           ; None        ; -9.300 ns ; RESET       ; POSITION[1]~reg0  ; LIFTCLK   ;
; N/A           ; None        ; -9.300 ns ; RESET       ; UDSIG~reg0        ; LIFTCLK   ;
; N/A           ; None        ; -9.300 ns ; RESET       ; \CTRLIFT:POS[1]   ; LIFTCLK   ;
+---------------+-------------+-----------+-------------+-------------------+-----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Thu Sep 28 10:11:23 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off THREEFLIFT -c THREEFLIFT
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "DOUT1[0]$latch" is a latch
    Warning: Node "DOUT1[1]$latch" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "LIFTCLK" is an undefined clock
    Info: Assuming node "BUTTONCLK" is an undefined clock
Info: Clock "LIFTCLK" has Internal fmax of 104.17 MHz between source register "POSITION[0]~reg0" and destination register "MYLIFT.doorclose" (period= 9.6 ns)
    Info: + Longest register to register delay is 8.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B4; Fanout = 28; REG Node = 'POSITION[0]~reg0'
        Info: 2: + IC(0.300 ns) + CELL(1.600 ns) = 1.900 ns; Loc. = LC3_B4; Fanout = 4; COMB Node = 'FDNLIGHT~117'
        Info: 3: + IC(1.000 ns) + CELL(1.600 ns) = 4.500 ns; Loc. = LC2_B3; Fanout = 1; COMB Node = 'MYLIFT~2563'
        Info: 4: + IC(0.300 ns) + CELL(1.400 ns) = 6.200 ns; Loc. = LC5_B3; Fanout = 1; COMB Node = 'MYLIFT~2567'
        Info: 5: + IC(1.200 ns) + CELL(1.100 ns) = 8.500 ns; Loc. = LC4_B9; Fanout = 5; REG Node = 'MYLIFT.doorclose'
        Info: Total cell delay = 5.700 ns ( 67.06 % )
        Info: Total interconnect delay = 2.800 ns ( 32.94 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "LIFTCLK" to destination register is 2.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 17; CLK Node = 'LIFTCLK'
            Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC4_B9; Fanout = 5; REG Node = 'MYLIFT.doorclose'
            Info: Total cell delay = 2.000 ns ( 83.33 % )
            Info: Total interconnect delay = 0.400 ns ( 16.67 % )
        Info: - Longest clock path from clock "LIFTCLK" to source register is 2.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 17; CLK Node = 'LIFTCLK'
            Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_B4; Fanout = 28; REG Node = 'POSITION[0]~reg0'
            Info: Total cell delay = 2.000 ns ( 83.33 % )
            Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Micro setup delay of destination is 0.600 ns
Info: Clock "BUTTONCLK" Internal fmax is restricted to 200.0 MHz between source register "STOPLIGHT[2]~reg0" and destination register "STOPLIGHT[2]~reg0"
    Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.800 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B28; Fanout = 8; REG Node = 'STOPLIGHT[2]~reg0'
            Info: 2: + IC(0.300 ns) + CELL(1.400 ns) = 1.700 ns; Loc. = LC6_B28; Fanout = 1; COMB Node = 'STOPLIGHT~280'
            Info: 3: + IC(0.300 ns) + CELL(0.800 ns) = 2.800 ns; Loc. = LC1_B28; Fanout = 8; REG Node = 'STOPLIGHT[2]~reg0'
            Info: Total cell delay = 2.200 ns ( 78.57 % )
            Info: Total interconnect delay = 0.600 ns ( 21.43 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "BUTTONCLK" to destination register is 2.400 ns
                Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 7; CLK Node = 'BUTTONCLK'
                Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_B28; Fanout = 8; REG Node = 'STOPLIGHT[2]~reg0'
                Info: Total cell delay = 2.000 ns ( 83.33 % )
                Info: Total interconnect delay = 0.400 ns ( 16.67 % )
            Info: - Longest clock path from clock "BUTTONCLK" to source register is 2.400 ns
                Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 7; CLK Node = 'BUTTONCLK'
                Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_B28; Fanout = 8; REG Node = 'STOPLIGHT[2]~reg0'
                Info: Total cell delay = 2.000 ns ( 83.33 % )
                Info: Total interconnect delay = 0.400 ns ( 16.67 % )
        Info: + Micro clock to output delay of source is 0.500 ns
        Info: + Micro setup delay of destination is 0.600 ns
Info: tsu for register "POSITION[0]~reg0" (data pin = "RESET", clock pin = "LIFTCLK") is 11.200 ns
    Info: + Longest pin to register delay is 13.000 ns
        Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_19; Fanout = 21; PIN Node = 'RESET'
        Info: 2: + IC(4.400 ns) + CELL(1.400 ns) = 10.700 ns; Loc. = LC5_B8; Fanout = 4; COMB Node = 'POSITION[0]~88'
        Info: 3: + IC(1.300 ns) + CELL(1.000 ns) = 13.000 ns; Loc. = LC1_B4; Fanout = 28; REG Node = 'POSITION[0]~reg0'
        Info: Total cell delay = 7.300 ns ( 56.15 % )
        Info: Total interconnect delay = 5.700 ns ( 43.85 % )
    Info: + Micro setup delay of destination is 0.600 ns
    Info: - Shortest clock path from clock "LIFTCLK" to destination register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 17; CLK Node = 'LIFTCLK'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_B4; Fanout = 28; REG Node = 'POSITION[0]~reg0'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
Info: tco from clock "LIFTCLK" to destination pin "UDSIG" through register "UDSIG~reg0" is 12.200 ns
    Info: + Longest clock path from clock "LIFTCLK" to source register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 17; CLK Node = 'LIFTCLK'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC4_B3; Fanout = 13; REG Node = 'UDSIG~reg0'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Longest register to pin delay is 9.300 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B3; Fanout = 13; REG Node = 'UDSIG~reg0'
        Info: 2: + IC(3.000 ns) + CELL(6.300 ns) = 9.300 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'UDSIG'
        Info: Total cell delay = 6.300 ns ( 67.74 % )
        Info: Total interconnect delay = 3.000 ns ( 32.26 % )
Info: th for register "STOPLIGHT[1]~reg0" (data pin = "STOP1BUTTON", clock pin = "BUTTONCLK") is -5.200 ns
    Info: + Longest clock path from clock "BUTTONCLK" to destination register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 7; CLK Node = 'BUTTONCLK'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC3_B28; Fanout = 8; REG Node = 'STOPLIGHT[1]~reg0'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro hold delay of destination is 1.300 ns
    Info: - Shortest pin to register delay is 8.900 ns
        Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_13; Fanout = 3; PIN Node = 'STOP1BUTTON'
        Info: 2: + IC(3.200 ns) + CELL(0.800 ns) = 8.900 ns; Loc. = LC3_B28; Fanout = 8; REG Node = 'STOPLIGHT[1]~reg0'
        Info: Total cell delay = 5.700 ns ( 64.04 % )
        Info: Total interconnect delay = 3.200 ns ( 35.96 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 4 warnings
    Info: Allocated 108 megabytes of memory during processing
    Info: Processing ended: Thu Sep 28 10:11:25 2006
    Info: Elapsed time: 00:00:02