dds.hier_info

基于飓风1 fpga 和stc单片机的dds信号源 程序是自己些的 能用 最大频率是2M

|dds
wr <= inst5.DB_MAX_OUTPUT_PORT_TYPE
clock => f5mhz:inst2.clk50m
dacba <= <GND>
cs <= <GND>
da[0] <= sine_rom:inst.q[0]
da[1] <= sine_rom:inst.q[1]
da[2] <= sine_rom:inst.q[2]
da[3] <= sine_rom:inst.q[3]
da[4] <= sine_rom:inst.q[4]
da[5] <= sine_rom:inst.q[5]
da[6] <= sine_rom:inst.q[6]
da[7] <= sine_rom:inst.q[7]
mcuclk => receive_f:inst4.clk
mcuenable => receive_f:inst4.enable
fre[0] => receive_f:inst4.fre[0]
fre[1] => receive_f:inst4.fre[1]
fre[2] => receive_f:inst4.fre[2]
fre[3] => receive_f:inst4.fre[3]
fre[4] => receive_f:inst4.fre[4]
fre[5] => receive_f:inst4.fre[5]
fre[6] => receive_f:inst4.fre[6]
fre[7] => receive_f:inst4.fre[7]


|dds|f5mhz:inst2
clk50m => count[2].CLK
clk50m => count[1].CLK
clk50m => count[0].CLK
clk50m => clk5m~reg0.CLK
clk5m <= clk5m~reg0.DB_MAX_OUTPUT_PORT_TYPE


|dds|sine_rom:inst
address[0] => address[0]~9.IN1
address[1] => address[1]~8.IN1
address[2] => address[2]~7.IN1
address[3] => address[3]~6.IN1
address[4] => address[4]~5.IN1
address[5] => address[5]~4.IN1
address[6] => address[6]~3.IN1
address[7] => address[7]~2.IN1
address[8] => address[8]~1.IN1
address[9] => address[9]~0.IN1
clock => clock~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a


|dds|sine_rom:inst|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_lu21:auto_generated.address_a[0]
address_a[1] => altsyncram_lu21:auto_generated.address_a[1]
address_a[2] => altsyncram_lu21:auto_generated.address_a[2]
address_a[3] => altsyncram_lu21:auto_generated.address_a[3]
address_a[4] => altsyncram_lu21:auto_generated.address_a[4]
address_a[5] => altsyncram_lu21:auto_generated.address_a[5]
address_a[6] => altsyncram_lu21:auto_generated.address_a[6]
address_a[7] => altsyncram_lu21:auto_generated.address_a[7]
address_a[8] => altsyncram_lu21:auto_generated.address_a[8]
address_a[9] => altsyncram_lu21:auto_generated.address_a[9]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_lu21:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_lu21:auto_generated.q_a[0]
q_a[1] <= altsyncram_lu21:auto_generated.q_a[1]
q_a[2] <= altsyncram_lu21:auto_generated.q_a[2]
q_a[3] <= altsyncram_lu21:auto_generated.q_a[3]
q_a[4] <= altsyncram_lu21:auto_generated.q_a[4]
q_a[5] <= altsyncram_lu21:auto_generated.q_a[5]
q_a[6] <= altsyncram_lu21:auto_generated.q_a[6]
q_a[7] <= altsyncram_lu21:auto_generated.q_a[7]
q_b[0] <= <GND>


|dds|sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT


|dds|high10:inst3
in20[0] => ~NO_FANOUT~
in20[1] => ~NO_FANOUT~
in20[2] => ~NO_FANOUT~
in20[3] => ~NO_FANOUT~
in20[4] => ~NO_FANOUT~
in20[5] => ~NO_FANOUT~
in20[6] => ~NO_FANOUT~
in20[7] => ~NO_FANOUT~
in20[8] => ~NO_FANOUT~
in20[9] => ~NO_FANOUT~
in20[10] => out10[0].DATAIN
in20[11] => out10[1].DATAIN
in20[12] => out10[2].DATAIN
in20[13] => out10[3].DATAIN
in20[14] => out10[4].DATAIN
in20[15] => out10[5].DATAIN
in20[16] => out10[6].DATAIN
in20[17] => out10[7].DATAIN
in20[18] => out10[8].DATAIN
in20[19] => out10[9].DATAIN
out10[0] <= in20[10].DB_MAX_OUTPUT_PORT_TYPE
out10[1] <= in20[11].DB_MAX_OUTPUT_PORT_TYPE
out10[2] <= in20[12].DB_MAX_OUTPUT_PORT_TYPE
out10[3] <= in20[13].DB_MAX_OUTPUT_PORT_TYPE
out10[4] <= in20[14].DB_MAX_OUTPUT_PORT_TYPE
out10[5] <= in20[15].DB_MAX_OUTPUT_PORT_TYPE
out10[6] <= in20[16].DB_MAX_OUTPUT_PORT_TYPE
out10[7] <= in20[17].DB_MAX_OUTPUT_PORT_TYPE
out10[8] <= in20[18].DB_MAX_OUTPUT_PORT_TYPE
out10[9] <= in20[19].DB_MAX_OUTPUT_PORT_TYPE


|dds|add:inst1
clock => clock~0.IN1
dataa[0] => dataa[0]~19.IN1
dataa[1] => dataa[1]~18.IN1
dataa[2] => dataa[2]~17.IN1
dataa[3] => dataa[3]~16.IN1
dataa[4] => dataa[4]~15.IN1
dataa[5] => dataa[5]~14.IN1
dataa[6] => dataa[6]~13.IN1
dataa[7] => dataa[7]~12.IN1
dataa[8] => dataa[8]~11.IN1
dataa[9] => dataa[9]~10.IN1
dataa[10] => dataa[10]~9.IN1
dataa[11] => dataa[11]~8.IN1
dataa[12] => dataa[12]~7.IN1
dataa[13] => dataa[13]~6.IN1
dataa[14] => dataa[14]~5.IN1
dataa[15] => dataa[15]~4.IN1
dataa[16] => dataa[16]~3.IN1
dataa[17] => dataa[17]~2.IN1
dataa[18] => dataa[18]~1.IN1
dataa[19] => dataa[19]~0.IN1
datab[0] => datab[0]~19.IN1
datab[1] => datab[1]~18.IN1
datab[2] => datab[2]~17.IN1
datab[3] => datab[3]~16.IN1
datab[4] => datab[4]~15.IN1
datab[5] => datab[5]~14.IN1
datab[6] => datab[6]~13.IN1
datab[7] => datab[7]~12.IN1
datab[8] => datab[8]~11.IN1
datab[9] => datab[9]~10.IN1
datab[10] => datab[10]~9.IN1
datab[11] => datab[11]~8.IN1
datab[12] => datab[12]~7.IN1
datab[13] => datab[13]~6.IN1
datab[14] => datab[14]~5.IN1
datab[15] => datab[15]~4.IN1
datab[16] => datab[16]~3.IN1
datab[17] => datab[17]~2.IN1
datab[18] => datab[18]~1.IN1
datab[19] => datab[19]~0.IN1
result[0] <= lpm_add_sub:lpm_add_sub_component.result
result[1] <= lpm_add_sub:lpm_add_sub_component.result
result[2] <= lpm_add_sub:lpm_add_sub_component.result
result[3] <= lpm_add_sub:lpm_add_sub_component.result
result[4] <= lpm_add_sub:lpm_add_sub_component.result
result[5] <= lpm_add_sub:lpm_add_sub_component.result
result[6] <= lpm_add_sub:lpm_add_sub_component.result
result[7] <= lpm_add_sub:lpm_add_sub_component.result
result[8] <= lpm_add_sub:lpm_add_sub_component.result
result[9] <= lpm_add_sub:lpm_add_sub_component.result
result[10] <= lpm_add_sub:lpm_add_sub_component.result
result[11] <= lpm_add_sub:lpm_add_sub_component.result
result[12] <= lpm_add_sub:lpm_add_sub_component.result
result[13] <= lpm_add_sub:lpm_add_sub_component.result
result[14] <= lpm_add_sub:lpm_add_sub_component.result
result[15] <= lpm_add_sub:lpm_add_sub_component.result
result[16] <= lpm_add_sub:lpm_add_sub_component.result
result[17] <= lpm_add_sub:lpm_add_sub_component.result
result[18] <= lpm_add_sub:lpm_add_sub_component.result
result[19] <= lpm_add_sub:lpm_add_sub_component.result


|dds|add:inst1|lpm_add_sub:lpm_add_sub_component
dataa[0] => addcore:adder1[0].dataa[0]
dataa[1] => addcore:adder1[0].dataa[1]
dataa[2] => addcore:adder1[0].dataa[2]
dataa[3] => addcore:adder1[0].dataa[3]
dataa[4] => addcore:adder1[0].dataa[4]
dataa[5] => addcore:adder1[0].dataa[5]
dataa[6] => addcore:adder1[0].dataa[6]
dataa[7] => addcore:adder1[0].dataa[7]
dataa[8] => addcore:adder1[0].dataa[8]
dataa[9] => addcore:adder1[0].dataa[9]
dataa[10] => addcore:adder1_0[1].dataa[0]
dataa[11] => addcore:adder1_0[1].dataa[1]
dataa[12] => addcore:adder1_0[1].dataa[2]
dataa[13] => addcore:adder1_0[1].dataa[3]
dataa[14] => addcore:adder1_0[1].dataa[4]
dataa[15] => addcore:adder1_0[1].dataa[5]
dataa[16] => addcore:adder1_0[1].dataa[6]
dataa[17] => addcore:adder1_0[1].dataa[7]
dataa[18] => addcore:adder1_0[1].dataa[8]
dataa[19] => addcore:adder1_0[1].dataa[9]
dataa[19] => bypassff:sign_ff[0].d[1]
datab[0] => addcore:adder1[0].datab[0]
datab[1] => addcore:adder1[0].datab[1]
datab[2] => addcore:adder1[0].datab[2]
datab[3] => addcore:adder1[0].datab[3]
datab[4] => addcore:adder1[0].datab[4]
datab[5] => addcore:adder1[0].datab[5]
datab[6] => addcore:adder1[0].datab[6]
datab[7] => addcore:adder1[0].datab[7]
datab[8] => addcore:adder1[0].datab[8]
datab[9] => addcore:adder1[0].datab[9]
datab[10] => addcore:adder1_0[1].datab[0]
datab[11] => addcore:adder1_0[1].datab[1]
datab[12] => addcore:adder1_0[1].datab[2]
datab[13] => addcore:adder1_0[1].datab[3]
datab[14] => addcore:adder1_0[1].datab[4]
datab[15] => addcore:adder1_0[1].datab[5]
datab[16] => addcore:adder1_0[1].datab[6]
datab[17] => addcore:adder1_0[1].datab[7]
datab[18] => addcore:adder1_0[1].datab[8]
datab[19] => addcore:adder1_0[1].datab[9]
datab[19] => bypassff:sign_ff[0].d[0]
cin => ~NO_FANOUT~