dds.hif

基于飓风1 fpga 和stc单片机的dds信号源 程序是自己些的 能用 最大频率是2M

Version 6.0 Build 178 04/27/2006 SJ Full Version
35
1731
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
f5mhz
# storage
db|dds.(0).cnf
db|dds.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
f5mhz.v
73ded09069f94a3f64f03eecb5785f42
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
f5mhz:inst2
}
# end
# entity
altsyncram_lu21
# storage
db|dds.(4).cnf
db|dds.(4).cnf
# case_insensitive
# source_file
db|altsyncram_lu21.tdf
f5272b1238bae42d7c24ebcdd2e2b9a
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
sine.mif
9127849e84dd14eea0ed076cea165
}
# end
# entity
high10
# storage
db|dds.(5).cnf
db|dds.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
high10.v
aec9cd1b39b1bb4afc5bc7379e1aa77
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
add
# storage
db|dds.(6).cnf
db|dds.(6).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
add.v
80e6cf76dae953ca931febe60f5031
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
receive_f
# storage
db|dds.(20).cnf
db|dds.(20).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
receive_f.v
63b2f3a73a569631ae2fb79a941e81
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
cntr_fbg
# storage
db|dds.(33).cnf
db|dds.(33).cnf
# case_insensitive
# source_file
db|cntr_fbg.tdf
39dad42697bb2063edb7ffb6391b66e5
6
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
clk_en
-1
3
aset
-1
3
}
# end
# entity
cntr_ekf
# storage
db|dds.(36).cnf
db|dds.(36).cnf
# case_insensitive
# source_file
db|cntr_ekf.tdf
e5492323d246543c6af2abd6715f3e10
6
# used_port {
sclr
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# end
# entity
cmpr_gnh
# storage
db|dds.(38).cnf
db|dds.(38).cnf
# case_insensitive
# source_file
db|cmpr_gnh.tdf
9604e9026598a51871b418c9b113c7
6
# used_port {
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab10
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa10
-1
3
dataa1
-1
3
dataa0
-1
3
aeb
-1
3
}
# end
# entity
cntr_ngh
# storage
db|dds.(41).cnf
db|dds.(41).cnf
# case_insensitive
# source_file
db|cntr_ngh.tdf
7d665edcda6cec6ca414279189d0f0
6
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
cout
-1
3
clock
-1
3
clk_en
-1
3
aclr
-1
3
}
# end
# entity
altsyncram_jji2
# storage
db|dds.(44).cnf
db|dds.(44).cnf
# case_insensitive
# source_file
db|altsyncram_jji2.tdf
ab5fa4564233e0ea8e441d80e8c5d61b
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
none
0
}
# end
# entity
cntr_ufe
# storage
db|dds.(47).cnf
db|dds.(47).cnf
# case_insensitive
# source_file
db|cntr_ufe.tdf
a3e041d099ad68998347e944a9d9
6
# used_port {
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
aclr
-1
3
}
# end
# entity
cntr_daf
# storage
db|dds.(49).cnf
db|dds.(49).cnf
# case_insensitive
# source_file
db|cntr_daf.tdf
664470d9d586c66c104c6db7522211d
6
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
clk_en
-1
3
aclr
-1
3
}
# end
# entity
decode_ogi
# storage
db|dds.(57).cnf
db|dds.(57).cnf
# case_insensitive
# source_file
db|decode_ogi.tdf
ffc7173ea4e253ca8971cc1a77d92062
6
# used_port {
eq7
-1
3
eq6
-1
3
eq5
-1
3
eq4
-1
3
eq3
-1
3
eq2
-1
3
eq1
-1
3
eq0
-1
3
enable
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
clken
-1
3
aclr
-1
3
}
# end
# entity
dds
# storage
db|dds.(1).cnf
db|dds.(1).cnf
# case_insensitive
# source_file
dds.bdf
a11e937168dfa84a7c8568ca075b9cc
24
# hierarchies {
|
}
# end
# entity
sine_rom
# storage
db|dds.(2).cnf
db|dds.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
sine_rom.v
f2ac93dc214da8f43eade953541aaa
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
sine_rom:inst
}
# end
# entity
altsyncram
# storage
db|dds.(3).cnf
db|dds.(3).cnf
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
12
PARAMETER_DEC
USR
NUMWORDS_A
4096
PARAMETER_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
D:/temp/temp/sine.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_q341
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a
-1
3
clock0
-1
3
address_a
-1
3
wren_b
-1
1
wren_a
-1
1
addressstall_b
-1
1
addressstall_a
-1
1
aclr1
-1
1
aclr0
-1
1
rden_b
-1
2
data_b
-1
2
data_a
-1
2
clocken1
-1
2
clocken0
-1
2
clock1
-1
2
byteena_b
-1
2
byteena_a
-1
2
address_b
-1
2
}
# include_file {
..|..|..|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|..|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|..|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|..|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
..|..|..|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|..|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
..|..|..|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
sine_rom:inst|altsyncram:altsyncram_component
}
# end
# complete