dds.map.qmsg

基于飓风1 fpga 和stc单片机的dds信号源 程序是自己些的 能用 最大频率是2M

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 13 22:03:57 2007 " "Info: Processing started: Thu Dec 13 22:03:57 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dds -c dds " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dds -c dds" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f5mhz.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file f5mhz.v" { { "Info" "ISGN_ENTITY_NAME" "1 f5mhz " "Info: Found entity 1: f5mhz" {  } { { "f5mhz.v" "" { Text "D:/Program/Quartus2/dds/f5mhz.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "high10.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file high10.v" { { "Info" "ISGN_ENTITY_NAME" "1 high10 " "Info: Found entity 1: high10" {  } { { "high10.v" "" { Text "D:/Program/Quartus2/dds/high10.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "receive_f.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file receive_f.v" { { "Info" "ISGN_ENTITY_NAME" "1 receive_f " "Info: Found entity 1: receive_f" {  } { { "receive_f.v" "" { Text "D:/Program/Quartus2/dds/receive_f.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dds.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file dds.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 dds " "Info: Found entity 1: dds" {  } { { "dds.bdf" "" { Schematic "D:/Program/Quartus2/dds/dds.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddsf.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ddsf.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ddsf " "Info: Found entity 1: ddsf" {  } { { "ddsf.bdf" "" { Schematic "D:/Program/Quartus2/dds/ddsf.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dds " "Info: Elaborating entity \"dds\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "f5mhz f5mhz:inst2 " "Info: Elaborating entity \"f5mhz\" for hierarchy \"f5mhz:inst2\"" {  } { { "dds.bdf" "inst2" { Schematic "D:/Program/Quartus2/dds/dds.bdf" { { 0 376 496 96 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sine_rom.v 1 1 " "Warning: Using design file sine_rom.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sine_rom " "Info: Found entity 1: sine_rom" {  } { { "sine_rom.v" "" { Text "D:/Program/Quartus2/dds/sine_rom.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sine_rom sine_rom:inst " "Info: Elaborating entity \"sine_rom\" for hierarchy \"sine_rom:inst\"" {  } { { "dds.bdf" "inst" { Schematic "D:/Program/Quartus2/dds/dds.bdf" { { 200 576 736 280 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../altera/quartus60/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus60/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 426 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram sine_rom:inst\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"sine_rom:inst\|altsyncram:altsyncram_component\"" {  } { { "sine_rom.v" "altsyncram_component" { Text "D:/Program/Quartus2/dds/sine_rom.v" 67 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "sine_rom:inst\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"sine_rom:inst\|altsyncram:altsyncram_component\"" {  } { { "sine_rom.v" "" { Text "D:/Program/Quartus2/dds/sine_rom.v" 67 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_q341.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_q341.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_q341 " "Info: Found entity 1: altsyncram_q341" {  } { { "db/altsyncram_q341.tdf" "" { Text "D:/Program/Quartus2/dds/db/altsyncram_q341.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_q341 sine_rom:inst\|altsyncram:altsyncram_component\|altsyncram_q341:auto_generated " "Info: Elaborating entity \"altsyncram_q341\" for hierarchy \"sine_rom:inst\|altsyncram:altsyncram_component\|altsyncram_q341:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Error" "ECDB_CDB_FILE_NOT_FOUND_FOR_ROM" "D:/temp/temp/sine.mif  " "Error: Can't find Memory Initialization File or Hexadecimal (Intel-Format) File D:/temp/temp/sine.mif for ROM instance " {  } { { "db/altsyncram_q341.tdf" "" { Text "D:/Program/Quartus2/dds/db/altsyncram_q341.tdf" 43 2 0 } }  } 0 0 "Can't find Memory Initialization File or Hexadecimal (Intel-Format) File %1!s! for ROM instance %2!s!" 0 0}
{ "Error" "ESGN_USER_HIER_ELABORATION_FAILURE" "sine_rom:inst\|altsyncram:altsyncram_component\|altsyncram_q341:auto_generated " "Error: Can't elaborate user hierarchy \"sine_rom:inst\|altsyncram:altsyncram_component\|altsyncram_q341:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } }  } 0 0 "Can't elaborate user hierarchy \"%1!s!\"" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 1  Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 1 warning" { { "Error" "EQEXE_END_BANNER_TIME" "Thu Dec 13 22:04:02 2007 " "Error: Processing ended: Thu Dec 13 22:04:02 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:07 " "Error: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}