dds.tan.qmsg

基于飓风1 fpga 和stc单片机的dds信号源 程序是自己些的 能用 最大频率是2M

{ "Info" "ITDB_FULL_TCO_RESULT" "clock da\[3\] sine_rom:inst\|altsyncram:altsyncram_component\|altsyncram_lu21:auto_generated\|q_a\[3\] 12.827 ns memory " "Info: tco from clock \"clock\" to destination pin \"da\[3\]\" through memory \"sine_rom:inst\|altsyncram:altsyncram_component\|altsyncram_lu21:auto_generated\|q_a\[3\]\" is 12.827 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 7.182 ns + Longest memory " "Info: + Longest clock path from clock \"clock\" to source memory is 7.182 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_93 171 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 171; CLK Node = 'clock'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "dds.bdf" "" { Schematic "D:/Program/Quartus2/dds/dds.bdf" { { -88 48 216 -72 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns f5mhz:inst2\|clk5m 2 REG LC_X8_Y6_N4 52 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N4; Fanout = 52; REG Node = 'f5mhz:inst2\|clk5m'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.495 ns" { clock f5mhz:inst2|clk5m } "NODE_NAME" } } { "f5mhz.v" "" { Text "D:/Program/Quartus2/dds/f5mhz.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.510 ns) + CELL(0.708 ns) 7.182 ns sine_rom:inst\|altsyncram:altsyncram_component\|altsyncram_lu21:auto_generated\|q_a\[3\] 3 MEM M4K_X13_Y9 2 " "Info: 3: + IC(3.510 ns) + CELL(0.708 ns) = 7.182 ns; Loc. = M4K_X13_Y9; Fanout = 2; MEM Node = 'sine_rom:inst\|altsyncram:altsyncram_component\|altsyncram_lu21:auto_generated\|q_a\[3\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.218 ns" { f5mhz:inst2|clk5m sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[3] } "NODE_NAME" } } { "db/altsyncram_lu21.tdf" "" { Text "D:/Program/Quartus2/dds/db/altsyncram_lu21.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.112 ns ( 43.33 % ) " "Info: Total cell delay = 3.112 ns ( 43.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.070 ns ( 56.67 % ) " "Info: Total interconnect delay = 4.070 ns ( 56.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.182 ns" { clock f5mhz:inst2|clk5m sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[3] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.182 ns" { clock clock~out0 f5mhz:inst2|clk5m sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[3] } { 0.000ns 0.000ns 0.560ns 3.510ns } { 0.000ns 1.469ns 0.935ns 0.708ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_lu21.tdf" "" { Text "D:/Program/Quartus2/dds/db/altsyncram_lu21.tdf" 40 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.995 ns + Longest memory pin " "Info: + Longest memory to pin delay is 4.995 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.104 ns) 0.104 ns sine_rom:inst\|altsyncram:altsyncram_component\|altsyncram_lu21:auto_generated\|q_a\[3\] 1 MEM M4K_X13_Y9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.104 ns) = 0.104 ns; Loc. = M4K_X13_Y9; Fanout = 2; MEM Node = 'sine_rom:inst\|altsyncram:altsyncram_component\|altsyncram_lu21:auto_generated\|q_a\[3\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[3] } "NODE_NAME" } } { "db/altsyncram_lu21.tdf" "" { Text "D:/Program/Quartus2/dds/db/altsyncram_lu21.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.767 ns) + CELL(2.124 ns) 4.995 ns da\[3\] 2 PIN PIN_105 0 " "Info: 2: + IC(2.767 ns) + CELL(2.124 ns) = 4.995 ns; Loc. = PIN_105; Fanout = 0; PIN Node = 'da\[3\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.891 ns" { sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[3] da[3] } "NODE_NAME" } } { "dds.bdf" "" { Schematic "D:/Program/Quartus2/dds/dds.bdf" { { 232 792 968 248 "da\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.228 ns ( 44.60 % ) " "Info: Total cell delay = 2.228 ns ( 44.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.767 ns ( 55.40 % ) " "Info: Total interconnect delay = 2.767 ns ( 55.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.995 ns" { sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[3] da[3] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "4.995 ns" { sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[3] da[3] } { 0.000ns 2.767ns } { 0.104ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.182 ns" { clock f5mhz:inst2|clk5m sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[3] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.182 ns" { clock clock~out0 f5mhz:inst2|clk5m sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[3] } { 0.000ns 0.000ns 0.560ns 3.510ns } { 0.000ns 1.469ns 0.935ns 0.708ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.995 ns" { sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[3] da[3] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "4.995 ns" { sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[3] da[3] } { 0.000ns 2.767ns } { 0.104ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "altera_internal_jtag~TDO altera_reserved_tdo 2.124 ns Longest " "Info: Longest tpd from source pin \"altera_internal_jtag~TDO\" to destination pin \"altera_reserved_tdo\" is 2.124 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TDO 1 PIN JTAG_X1_Y6_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 1; PIN Node = 'altera_internal_jtag~TDO'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.124 ns) 2.124 ns altera_reserved_tdo 2 PIN PIN_90 0 " "Info: 2: + IC(0.000 ns) + CELL(2.124 ns) = 2.124 ns; Loc. = PIN_90; Fanout = 0; PIN Node = 'altera_reserved_tdo'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 100.00 % ) " "Info: Total cell delay = 2.124 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } { 0.000ns 0.000ns } { 0.000ns 2.124ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|lpm_shiftreg:trigger_condition_deserialize\|dffs\[26\] altera_internal_jtag altera_internal_jtag~TCKUTAP 3.173 ns register " "Info: th for register \"sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|lpm_shiftreg:trigger_condition_deserialize\|dffs\[26\]\" (data pin = \"altera_internal_jtag\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 3.173 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.272 ns + Longest register " "Info: + Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.272 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 231 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 231; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.561 ns) + CELL(0.711 ns) 5.272 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|lpm_shiftreg:trigger_condition_deserialize\|dffs\[26\] 2 REG LC_X15_Y8_N6 3 " "Info: 2: + IC(4.561 ns) + CELL(0.711 ns) = 5.272 ns; Loc. = LC_X15_Y8_N6; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|lpm_shiftreg:trigger_condition_deserialize\|dffs\[26\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[26] } "NODE_NAME" } } { "lpm_shiftreg.tdf" "" { Text "d:/program files/altera/quartus60/libraries/megafunctions/lpm_shiftreg.tdf" 54 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.49 % ) " "Info: Total cell delay = 0.711 ns ( 13.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.561 ns ( 86.51 % ) " "Info: Total interconnect delay = 4.561 ns ( 86.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[26] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[26] } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "lpm_shiftreg.tdf" "" { Text "d:/program files/altera/quartus60/libraries/megafunctions/lpm_shiftreg.tdf" 54 7 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.114 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.114 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag 1 PIN JTAG_X1_Y6_N1 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 9; PIN Node = 'altera_internal_jtag'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.999 ns) + CELL(0.115 ns) 2.114 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|lpm_shiftreg:trigger_condition_deserialize\|dffs\[26\] 2 REG LC_X15_Y8_N6 3 " "Info: 2: + IC(1.999 ns) + CELL(0.115 ns) = 2.114 ns; Loc. = LC_X15_Y8_N6; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|lpm_shiftreg:trigger_condition_deserialize\|dffs\[26\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.114 ns" { altera_internal_jtag sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[26] } "NODE_NAME" } } { "lpm_shiftreg.tdf" "" { Text "d:/program files/altera/quartus60/libraries/megafunctions/lpm_shiftreg.tdf" 54 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns ( 5.44 % ) " "Info: Total cell delay = 0.115 ns ( 5.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.999 ns ( 94.56 % ) " "Info: Total interconnect delay = 1.999 ns ( 94.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.114 ns" { altera_internal_jtag sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[26] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d: