dds.tan.qmsg

基于飓风1 fpga 和stc单片机的dds信号源 程序是自己些的 能用 最大频率是2M

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "mcuclk register register receive_f:inst4\|count.11 receive_f:inst4\|qout\[9\] 275.03 MHz Internal " "Info: Clock \"mcuclk\" Internal fmax is restricted to 275.03 MHz between source register \"receive_f:inst4\|count.11\" and destination register \"receive_f:inst4\|qout\[9\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.460 ns + Longest register register " "Info: + Longest register to register delay is 2.460 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns receive_f:inst4\|count.11 1 REG LC_X6_Y11_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y11_N2; Fanout = 2; REG Node = 'receive_f:inst4\|count.11'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { receive_f:inst4|count.11 } "NODE_NAME" } } { "receive_f.v" "" { Text "D:/Program/Quartus2/dds/receive_f.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.378 ns) 0.378 ns receive_f:inst4\|qout\[10\]~29 2 COMB LC_X6_Y11_N2 20 " "Info: 2: + IC(0.000 ns) + CELL(0.378 ns) = 0.378 ns; Loc. = LC_X6_Y11_N2; Fanout = 20; COMB Node = 'receive_f:inst4\|qout\[10\]~29'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.378 ns" { receive_f:inst4|count.11 receive_f:inst4|qout[10]~29 } "NODE_NAME" } } { "receive_f.v" "" { Text "D:/Program/Quartus2/dds/receive_f.v" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.215 ns) + CELL(0.867 ns) 2.460 ns receive_f:inst4\|qout\[9\] 3 REG LC_X5_Y10_N6 2 " "Info: 3: + IC(1.215 ns) + CELL(0.867 ns) = 2.460 ns; Loc. = LC_X5_Y10_N6; Fanout = 2; REG Node = 'receive_f:inst4\|qout\[9\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.082 ns" { receive_f:inst4|qout[10]~29 receive_f:inst4|qout[9] } "NODE_NAME" } } { "receive_f.v" "" { Text "D:/Program/Quartus2/dds/receive_f.v" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.245 ns ( 50.61 % ) " "Info: Total cell delay = 1.245 ns ( 50.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.215 ns ( 49.39 % ) " "Info: Total interconnect delay = 1.215 ns ( 49.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.460 ns" { receive_f:inst4|count.11 receive_f:inst4|qout[10]~29 receive_f:inst4|qout[9] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.460 ns" { receive_f:inst4|count.11 receive_f:inst4|qout[10]~29 receive_f:inst4|qout[9] } { 0.000ns 0.000ns 1.215ns } { 0.000ns 0.378ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mcuclk destination 2.768 ns + Shortest register " "Info: + Shortest clock path from clock \"mcuclk\" to destination register is 2.768 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mcuclk 1 CLK PIN_16 44 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 44; CLK Node = 'mcuclk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { mcuclk } "NODE_NAME" } } { "dds.bdf" "" { Schematic "D:/Program/Quartus2/dds/dds.bdf" { { 24 -120 48 40 "mcuclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.588 ns) + CELL(0.711 ns) 2.768 ns receive_f:inst4\|qout\[9\] 2 REG LC_X5_Y10_N6 2 " "Info: 2: + IC(0.588 ns) + CELL(0.711 ns) = 2.768 ns; Loc. = LC_X5_Y10_N6; Fanout = 2; REG Node = 'receive_f:inst4\|qout\[9\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.299 ns" { mcuclk receive_f:inst4|qout[9] } "NODE_NAME" } } { "receive_f.v" "" { Text "D:/Program/Quartus2/dds/receive_f.v" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.76 % ) " "Info: Total cell delay = 2.180 ns ( 78.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.588 ns ( 21.24 % ) " "Info: Total interconnect delay = 0.588 ns ( 21.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.768 ns" { mcuclk receive_f:inst4|qout[9] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.768 ns" { mcuclk mcuclk~out0 receive_f:inst4|qout[9] } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mcuclk source 2.768 ns - Longest register " "Info: - Longest clock path from clock \"mcuclk\" to source register is 2.768 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mcuclk 1 CLK PIN_16 44 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 44; CLK Node = 'mcuclk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { mcuclk } "NODE_NAME" } } { "dds.bdf" "" { Schematic "D:/Program/Quartus2/dds/dds.bdf" { { 24 -120 48 40 "mcuclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.588 ns) + CELL(0.711 ns) 2.768 ns receive_f:inst4\|count.11 2 REG LC_X6_Y11_N2 2 " "Info: 2: + IC(0.588 ns) + CELL(0.711 ns) = 2.768 ns; Loc. = LC_X6_Y11_N2; Fanout = 2; REG Node = 'receive_f:inst4\|count.11'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.299 ns" { mcuclk receive_f:inst4|count.11 } "NODE_NAME" } } { "receive_f.v" "" { Text "D:/Program/Quartus2/dds/receive_f.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.76 % ) " "Info: Total cell delay = 2.180 ns ( 78.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.588 ns ( 21.24 % ) " "Info: Total interconnect delay = 0.588 ns ( 21.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.768 ns" { mcuclk receive_f:inst4|count.11 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.768 ns" { mcuclk mcuclk~out0 receive_f:inst4|count.11 } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.768 ns" { mcuclk receive_f:inst4|qout[9] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.768 ns" { mcuclk mcuclk~out0 receive_f:inst4|qout[9] } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.768 ns" { mcuclk receive_f:inst4|count.11 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.768 ns" { mcuclk mcuclk~out0 receive_f:inst4|count.11 } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "receive_f.v" "" { Text "D:/Program/Quartus2/dds/receive_f.v" 7 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "receive_f.v" "" { Text "D:/Program/Quartus2/dds/receive_f.v" 35 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.460 ns" { receive_f:inst4|count.11 receive_f:inst4|qout[10]~29 receive_f:inst4|qout[9] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.460 ns" { receive_f:inst4|count.11 receive_f:inst4|qout[10]~29 receive_f:inst4|qout[9] } { 0.000ns 0.000ns 1.215ns } { 0.000ns 0.378ns 0.867ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.768 ns" { mcuclk receive_f:inst4|qout[9] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.768 ns" { mcuclk mcuclk~out0 receive_f:inst4|qout[9] } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.768 ns" { mcuclk receive_f:inst4|count.11 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.768 ns" { mcuclk mcuclk~out0 receive_f:inst4|count.11 } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { receive_f:inst4|qout[9] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { receive_f:inst4|qout[9] } {  } {  } } } { "receive_f.v" "" { Text "D:/Program/Quartus2/dds/receive_f.v" 35 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 register sld_hub:sld_hub_inst\|hub_tdo 130.11 MHz 7.686 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 130.11 MHz between source register \"sld_hub:sld_hub_inst\|jtag_debug_mode_usr1\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 7.686 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.620 ns + Longest register register " "Info: + Longest register to register delay is 3.620 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 1 REG LC_X20_Y5_N8 18 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y5_N8; Fanout = 18; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "../../../program files/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/program files/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 391 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.369 ns) + CELL(0.292 ns) 1.661 ns sld_signaltap:auto_signaltap_0\|comb~151 2 COMB LC_X21_Y7_N2 5 " "Info: 2: + IC(1.369 ns) + CELL(0.292 ns) = 1.661 ns; Loc. = LC_X21_Y7_N2; Fanout = 5; COMB Node = 'sld_signaltap:auto_signaltap_0\|comb~151'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.661 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_signaltap:auto_signaltap_0|comb~151 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.440 ns) + CELL(0.590 ns) 2.691 ns sld_hub:sld_hub_inst\|hub_tdo~450 3 COMB LC_X21_Y7_N4 1 " "Info: 3: + IC(0.440 ns) + CELL(0.590 ns) = 2.691 ns; Loc. = LC_X21_Y7_N4; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~450'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.030 ns" { sld_signaltap:auto_signaltap_0|comb~151 sld_hub:sld_hub_inst|hub_tdo~450 } "NODE_NAME" } } { "../../../program files/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/program files/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.478 ns) 3.620 ns sld_hub:sld_hub_inst\|hub_tdo 4 REG LC_X21_Y7_N8 1 " "Info: 4: + IC(0.451 ns) + CELL(0.478 ns) = 3.620 ns; Loc. = LC_X21_Y7_N8; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.929 ns" { sld_hub:sld_hub_inst|hub_tdo~450 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "../../../program files/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/program files/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.360 ns ( 37.57 % ) " "Info: Total cell delay = 1.360 ns ( 37.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.260 ns ( 62.43 % ) " "Info: Total interconnect delay = 2.260 ns ( 62.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.620 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_signaltap:auto_signaltap_0|comb~151 sld_hub:sld_hub_inst|hub_tdo~450 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.620 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_signaltap:auto_signaltap_0|comb~151 sld_hub:sld_hub_inst|hub_tdo~450 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.369ns 0.440ns 0.451ns } { 0.000ns 0.292ns 0.590ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.038 ns - Smallest " "Info: - Smallest clock skew is 0.038 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.272 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.272 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 231 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 231; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.561 ns) + CELL(0.711 ns) 5.272 ns sld_hub:sld_hub_inst\|hub_tdo 2 REG LC_X21_Y7_N8 1 " "Info: 2: + IC(4.561 ns) + CELL(0.711 ns) = 5.272 ns; Loc. = LC_X21_Y7_N8; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "../../../program files/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/program files/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.49 % ) " "Info: Total cell delay = 0.711 ns ( 13.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.561 ns ( 86.51 % ) " "Info: Total interconnect delay = 4.561 ns ( 86.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.234 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.234 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 231 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 231; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.523 ns) + CELL(0.711 ns) 5.234 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 2 REG LC_X20_Y5_N8 18 " "Info: 2: + IC(4.523 ns) + CELL(0.711 ns) = 5.234 ns; Loc. = LC_X20_Y5_N8; Fanout = 18; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.234 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "../../../program files/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/program files/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 391 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.58 % ) " "Info: Total cell delay = 0.711 ns ( 13.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.523 ns ( 86.42 % ) " "Info: Total interconnect delay = 4.523 ns ( 86.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.234 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "5.234 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 4.523ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.234 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "5.234 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 4.523ns } { 0.000ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../../../program files/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/program files/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 391 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "../../../program files/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/program files/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "../../../program files/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/program files/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 391 -1 0 } } { "../../../program files/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/program files/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.620 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_signaltap:auto_signaltap_0|comb~151 sld_hub:sld_hub_inst|hub_tdo~450 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.620 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_signaltap:auto_signaltap_0|comb~151 sld_hub:sld_hub_inst|hub_tdo~450 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.369ns 0.440ns 0.451ns } { 0.000ns 0.292ns 0.590ns 0.478ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.234 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "5.234 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 4.523ns } { 0.000ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "receive_f:inst4\|qtemp\[14\] fre\[6\] mcuclk 4.705 ns register " "Info: tsu for register \"receive_f:inst4\|qtemp\[14\]\" (data pin = \"fre\[6\]\", clock pin = \"mcuclk\") is 4.705 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.436 ns + Longest pin register " "Info: + Longest pin to register delay is 7.436 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns fre\[6\] 1 PIN PIN_2 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 2; PIN Node = 'fre\[6\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { fre[6] } "NODE_NAME" } } { "dds.bdf" "" { Schematic "D:/Program/Quartus2/dds/dds.bdf" { { 40 -120 48 56 "fre\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.852 ns) + CELL(0.115 ns) 7.436 ns receive_f:inst4\|qtemp\[14\] 2 REG LC_X4_Y11_N0 1 " "Info: 2: + IC(5.852 ns) + CELL(0.115 ns) = 7.436 ns; Loc. = LC_X4_Y11_N0; Fanout = 1; REG Node = 'receive_f:inst4\|qtemp\[14\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.967 ns" { fre[6] receive_f:inst4|qtemp[14] } "NODE_NAME" } } { "receive_f.v" "" { Text "D:/Program/Quartus2/dds/receive_f.v" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 21.30 % ) " "Info: Total cell delay = 1.584 ns ( 21.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.852 ns ( 78.70 % ) " "Info: Total interconnect delay = 5.852 ns ( 78.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.436 ns" { fre[6] receive_f:inst4|qtemp[14] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.436 ns" { fre[6] fre[6]~out0 receive_f:inst4|qtemp[14] } { 0.000ns 0.000ns 5.852ns } { 0.000ns 1.469ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "receive_f.v" "" { Text "D:/Program/Quartus2/dds/receive_f.v" 35 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mcuclk destination 2.768 ns - Shortest register " "Info: - Shortest clock path from clock \"mcuclk\" to destination register is 2.768 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mcuclk 1 CLK PIN_16 44 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 44; CLK Node = 'mcuclk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { mcuclk } "NODE_NAME" } } { "dds.bdf" "" { Schematic "D:/Program/Quartus2/dds/dds.bdf" { { 24 -120 48 40 "mcuclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.588 ns) + CELL(0.711 ns) 2.768 ns receive_f:inst4\|qtemp\[14\] 2 REG LC_X4_Y11_N0 1 " "Info: 2: + IC(0.588 ns) + CELL(0.711 ns) = 2.768 ns; Loc. = LC_X4_Y11_N0; Fanout = 1; REG Node = 'receive_f:inst4\|qtemp\[14\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.299 ns" { mcuclk receive_f:inst4|qtemp[14] } "NODE_NAME" } } { "receive_f.v" "" { Text "D:/Program/Quartus2/dds/receive_f.v" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.76 % ) " "Info: Total cell delay = 2.180 ns ( 78.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.588 ns ( 21.24 % ) " "Info: Total interconnect delay = 0.588 ns ( 21.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.768 ns" { mcuclk receive_f:inst4|qtemp[14] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.768 ns" { mcuclk mcuclk~out0 receive_f:inst4|qtemp[14] } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.436 ns" { fre[6] receive_f:inst4|qtemp[14] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.436 ns" { fre[6] fre[6]~out0 receive_f:inst4|qtemp[14] } { 0.000ns 0.000ns 5.852ns } { 0.000ns 1.469ns 0.115ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.768 ns" { mcuclk receive_f:inst4|qtemp[14] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.768 ns" { mcuclk mcuclk~out0 receive_f:inst4|qtemp[14] } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}