dds.tan.qmsg

基于飓风1 fpga 和stc单片机的dds信号源 程序是自己些的 能用 最大频率是2M

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "dds.bdf" "" { Schematic "D:/Program/Quartus2/dds/dds.bdf" { { -88 48 216 -72 "clock" "" } } } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "mcuclk " "Info: Assuming node \"mcuclk\" is an undefined clock" {  } { { "dds.bdf" "" { Schematic "D:/Program/Quartus2/dds/dds.bdf" { { 24 -120 48 40 "mcuclk" "" } } } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "mcuclk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "f5mhz:inst2\|clk5m " "Info: Detected ripple clock \"f5mhz:inst2\|clk5m\" as buffer" {  } { { "f5mhz.v" "" { Text "D:/Program/Quartus2/dds/f5mhz.v" 3 -1 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "f5mhz:inst2\|clk5m" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock memory sine_rom:inst\|altsyncram:altsyncram_component\|altsyncram_lu21:auto_generated\|q_a\[1\] register sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[1\] 145.94 MHz 6.852 ns Internal " "Info: Clock \"clock\" has Internal fmax of 145.94 MHz between source memory \"sine_rom:inst\|altsyncram:altsyncram_component\|altsyncram_lu21:auto_generated\|q_a\[1\]\" and destination register \"sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[1\]\" (period= 6.852 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.765 ns + Longest memory register " "Info: + Longest memory to register delay is 1.765 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.104 ns) 0.104 ns sine_rom:inst\|altsyncram:altsyncram_component\|altsyncram_lu21:auto_generated\|q_a\[1\] 1 MEM M4K_X13_Y10 2 " "Info: 1: + IC(0.000 ns) + CELL(0.104 ns) = 0.104 ns; Loc. = M4K_X13_Y10; Fanout = 2; MEM Node = 'sine_rom:inst\|altsyncram:altsyncram_component\|altsyncram_lu21:auto_generated\|q_a\[1\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[1] } "NODE_NAME" } } { "db/altsyncram_lu21.tdf" "" { Text "D:/Program/Quartus2/dds/db/altsyncram_lu21.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.546 ns) + CELL(0.115 ns) 1.765 ns sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[1\] 2 REG LC_X15_Y7_N8 3 " "Info: 2: + IC(1.546 ns) + CELL(0.115 ns) = 1.765 ns; Loc. = LC_X15_Y7_N8; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[1\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.661 ns" { sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[1] sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[1] } "NODE_NAME" } } { "../../../program files/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" "" { Text "D:/program files/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" 573 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.219 ns ( 12.41 % ) " "Info: Total cell delay = 0.219 ns ( 12.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.546 ns ( 87.59 % ) " "Info: Total interconnect delay = 1.546 ns ( 87.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.765 ns" { sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[1] sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[1] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "1.765 ns" { sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[1] sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[1] } { 0.000ns 1.546ns } { 0.104ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.400 ns - Smallest " "Info: - Smallest clock skew is -4.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.782 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_93 171 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 171; CLK Node = 'clock'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "dds.bdf" "" { Schematic "D:/Program/Quartus2/dds/dds.bdf" { { -88 48 216 -72 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[1\] 2 REG LC_X15_Y7_N8 3 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X15_Y7_N8; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[1\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.313 ns" { clock sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[1] } "NODE_NAME" } } { "../../../program files/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" "" { Text "D:/program files/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" 573 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clock sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[1] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { clock clock~out0 sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[1] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 7.182 ns - Longest memory " "Info: - Longest clock path from clock \"clock\" to source memory is 7.182 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_93 171 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 171; CLK Node = 'clock'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "dds.bdf" "" { Schematic "D:/Program/Quartus2/dds/dds.bdf" { { -88 48 216 -72 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns f5mhz:inst2\|clk5m 2 REG LC_X8_Y6_N4 52 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N4; Fanout = 52; REG Node = 'f5mhz:inst2\|clk5m'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.495 ns" { clock f5mhz:inst2|clk5m } "NODE_NAME" } } { "f5mhz.v" "" { Text "D:/Program/Quartus2/dds/f5mhz.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.510 ns) + CELL(0.708 ns) 7.182 ns sine_rom:inst\|altsyncram:altsyncram_component\|altsyncram_lu21:auto_generated\|q_a\[1\] 3 MEM M4K_X13_Y10 2 " "Info: 3: + IC(3.510 ns) + CELL(0.708 ns) = 7.182 ns; Loc. = M4K_X13_Y10; Fanout = 2; MEM Node = 'sine_rom:inst\|altsyncram:altsyncram_component\|altsyncram_lu21:auto_generated\|q_a\[1\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.218 ns" { f5mhz:inst2|clk5m sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[1] } "NODE_NAME" } } { "db/altsyncram_lu21.tdf" "" { Text "D:/Program/Quartus2/dds/db/altsyncram_lu21.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.112 ns ( 43.33 % ) " "Info: Total cell delay = 3.112 ns ( 43.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.070 ns ( 56.67 % ) " "Info: Total interconnect delay = 4.070 ns ( 56.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.182 ns" { clock f5mhz:inst2|clk5m sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[1] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.182 ns" { clock clock~out0 f5mhz:inst2|clk5m sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[1] } { 0.000ns 0.000ns 0.560ns 3.510ns } { 0.000ns 1.469ns 0.935ns 0.708ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clock sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[1] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { clock clock~out0 sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[1] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.182 ns" { clock f5mhz:inst2|clk5m sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[1] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.182 ns" { clock clock~out0 f5mhz:inst2|clk5m sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[1] } { 0.000ns 0.000ns 0.560ns 3.510ns } { 0.000ns 1.469ns 0.935ns 0.708ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_lu21.tdf" "" { Text "D:/Program/Quartus2/dds/db/altsyncram_lu21.tdf" 40 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "../../../program files/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" "" { Text "D:/program files/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" 573 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.765 ns" { sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[1] sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[1] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "1.765 ns" { sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[1] sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[1] } { 0.000ns 1.546ns } { 0.104ns 0.115ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clock sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[1] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { clock clock~out0 sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[1] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.182 ns" { clock f5mhz:inst2|clk5m sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[1] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.182 ns" { clock clock~out0 f5mhz:inst2|clk5m sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[1] } { 0.000ns 0.000ns 0.560ns 3.510ns } { 0.000ns 1.469ns 0.935ns 0.708ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}