dds.fit.qmsg

基于飓风1 fpga 和stc单片机的dds信号源 程序是自己些的 能用 最大频率是2M

{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.513 ns memory register " "Info: Estimated most critical path is memory to register delay of 1.513 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.104 ns) 0.104 ns sine_rom:inst\|altsyncram:altsyncram_component\|altsyncram_lu21:auto_generated\|q_a\[1\] 1 MEM M4K_X13_Y10 2 " "Info: 1: + IC(0.000 ns) + CELL(0.104 ns) = 0.104 ns; Loc. = M4K_X13_Y10; Fanout = 2; MEM Node = 'sine_rom:inst\|altsyncram:altsyncram_component\|altsyncram_lu21:auto_generated\|q_a\[1\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[1] } "NODE_NAME" } } { "db/altsyncram_lu21.tdf" "" { Text "D:/Program/Quartus2/dds/db/altsyncram_lu21.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.294 ns) + CELL(0.115 ns) 1.513 ns sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[1\] 2 REG LAB_X15_Y7 3 " "Info: 2: + IC(1.294 ns) + CELL(0.115 ns) = 1.513 ns; Loc. = LAB_X15_Y7; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[1\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.409 ns" { sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[1] sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[1] } "NODE_NAME" } } { "../../../program files/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" "" { Text "D:/program files/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" 573 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.219 ns ( 14.47 % ) " "Info: Total cell delay = 0.219 ns ( 14.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.294 ns ( 85.53 % ) " "Info: Total interconnect delay = 1.294 ns ( 85.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.513 ns" { sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[1] sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[1] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "4 4 " "Info: Average interconnect usage is 4% of the available device resources. Peak interconnect usage is 4%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x14_y0 x27_y14 " "Info: The peak interconnect region extends from location x14_y0 to location x27_y14" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Info: Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|CLR_SIGNAL " "Info: Node sld_hub:sld_hub_inst\|CLR_SIGNAL uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\] -- routed using non-global resources" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\]" } } } } { "../../../program files/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "D:/program files/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[8\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[8\] -- routed using non-global resources" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[8] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[8\]" } } } } { "../../../program files/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "D:/program files/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[8] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\] -- routed using non-global resources" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\]" } } } } { "../../../program files/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "D:/program files/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] -- routed using non-global resources" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\]" } } } } { "../../../program files/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "D:/program files/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|CLR_SIGNAL" } } } } { "../../../program files/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/program files/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 316 -1 0 } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "2 " "Warning: Following 2 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "dacba GND " "Info: Pin dacba has GND driving its datain port" {  } { { "dds.bdf" "" { Schematic "D:/Program/Quartus2/dds/dds.bdf" { { 56 760 936 72 "dacba" "" } } } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "dacba" } } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { dacba } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { dacba } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "cs GND " "Info: Pin cs has GND driving its datain port" {  } { { "dds.bdf" "" { Schematic "D:/Program/Quartus2/dds/dds.bdf" { { 80 760 936 96 "cs" "" } } } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cs" } } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cs } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cs } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue May 22 23:46:29 2007 " "Info: Processing ended: Tue May 22 23:46:29 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/Program/Quartus2/dds/dds.fit.smsg " "Info: Generated suppressed messages file D:/Program/Quartus2/dds/dds.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}