receive_f.v

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module receive_f(clk,fre,enable,qout);
input clk,enable;
input [7:0]fre;
output [19:0]qout;
reg[19:0]qout;
reg[19:0]qtemp;
reg[1:0]count;
always@(posedge clk)
begin
if(enable==1'b1)
begin
case (count)
2'd0:
begin
qtemp[7:0]<=fre;
count<=2'd1;
end
2'd1:
begin
qtemp[15:8]<=fre;
count<=2'd2;
end
2'd2:
begin
qtemp[19:16]<=fre[3:0];
count<=2'd3;
end
2'd3:
begin	
qout<=qtemp;
count<=2'd0;
end
endcase
end
end
endmodule