dds.tan.rpt

基于飓风1 fpga 和stc单片机的dds信号源 程序是自己些的 能用 最大频率是2M

; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                          ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name              ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock                        ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; mcuclk                       ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; altera_internal_jtag~TCKUTAP ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                                                                                                            ; To                                                                                                                                                   ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 145.94 MHz ( period = 6.852 ns )                    ; sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[1]                                                                                                                                                                             ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[1]                                                                                                 ; clock      ; clock    ; None                        ; None                      ; 1.765 ns                ;
; N/A                                     ; 152.60 MHz ( period = 6.553 ns )                    ; sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[2]                                                                                                                                                                             ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[2]                                                                                                 ; clock      ; clock    ; None                        ; None                      ; 1.466 ns                ;
; N/A                                     ; 155.04 MHz ( period = 6.450 ns )                    ; sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[0]                                                                                                                                                                             ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[0]                                                                                                 ; clock      ; clock    ; None                        ; None                      ; 1.349 ns                ;
; N/A                                     ; 156.42 MHz ( period = 6.393 ns )                    ; sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[3]                                                                                                                                                                             ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[3]                                                                                                 ; clock      ; clock    ; None                        ; None                      ; 1.306 ns                ;
; N/A                                     ; 156.57 MHz ( period = 6.387 ns )                    ; sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[4]                                                                                                                                                                             ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[4]                                                                                                 ; clock      ; clock    ; None                        ; None                      ; 1.300 ns                ;
; N/A                                     ; 156.84 MHz ( period = 6.376 ns )                    ; sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[6]                                                                                                                                                                             ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[6]                                                                                                 ; clock      ; clock    ; None                        ; None                      ; 1.289 ns                ;
; N/A                                     ; 159.46 MHz ( period = 6.271 ns )                    ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1|regoutff ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena ; clock      ; clock    ; None                        ; None                      ; 5.968 ns                ;
; N/A                                     ; 163.05 MHz ( period = 6.133 ns )                    ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1|regoutff ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena ; clock      ; clock    ; None                        ; None                      ; 5.830 ns                ;
; N/A                                     ; 165.21 MHz ( period = 6.053 ns )                    ; add:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10]                                                                                                                                                             ; add:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[9]                                                 ; clock      ; clock    ; None                        ; None                      ; 5.807 ns                ;
; N/A                                     ; 165.62 MHz ( period = 6.038 ns )                    ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1|regoutff ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_state_machine:sm1|post_trigger_count_enable                                       ; clock      ; clock    ; None                        ; None                      ; 5.735 ns                ;
; N/A                                     ; 165.73 MHz ( period = 6.034 ns )                    ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1|regoutff ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0]                                               ; clock      ; clock    ; None                        ; None                      ; 5.731 ns                ;