dds.tan.rpt

基于飓风1 fpga 和stc单片机的dds信号源 程序是自己些的 能用 最大频率是2M

Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
+---------------------------------------------+-------+---------------+------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                                    ; From                                                                                ; To                                                                                                                                                                                                    ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 4.705 ns                                       ; fre[6]                                                                              ; receive_f:inst4|qtemp[14]                                                                                                                                                                             ; --                           ; mcuclk                       ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 12.827 ns                                      ; sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[3] ; da[3]                                                                                                                                                                                                 ; clock                        ; --                           ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 2.124 ns                                       ; altera_internal_jtag~TDO                                                            ; altera_reserved_tdo                                                                                                                                                                                   ; --                           ; --                           ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 3.173 ns                                       ; altera_internal_jtag                                                                ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[26] ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 130.11 MHz ( period = 7.686 ns )               ; sld_hub:sld_hub_inst|jtag_debug_mode_usr1                                           ; sld_hub:sld_hub_inst|hub_tdo                                                                                                                                                                          ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'clock'                        ; N/A   ; None          ; 145.94 MHz ( period = 6.852 ns )               ; sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[1] ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[1]                                                                                                                                                  ; clock                        ; clock                        ; 0            ;
; Clock Setup: 'mcuclk'                       ; N/A   ; None          ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; receive_f:inst4|count.11                                                            ; receive_f:inst4|qout[5]                                                                                                                                                                               ; mcuclk                       ; mcuclk                       ; 0            ;
; Total number of failed paths                ;       ;               ;                                                ;                                                                                     ;                                                                                                                                                                                                       ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;