dds.sim.rpt

基于飓风1 fpga 和stc单片机的dds信号源 程序是自己些的 能用 最大频率是2M

; Preserve fewer signal transitions to reduce memory requirements                            ; On         ; On            ;
; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE ; INPUT_EDGE    ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off        ; Off           ;
; Overwrite Waveform Inputs With Simulation Outputs                                          ; On         ;               ;
; Glitch Filtering                                                                           ; Off        ; Off           ;
+--------------------------------------------------------------------------------------------+------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+----------------------------------------------------------------------------------------------+
; |dds|sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|ALTSYNCRAM ;
+----------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      14.29 % ;
; Total nodes checked                                 ; 105          ;
; Total output ports checked                          ; 154          ;
; Total output ports with complete 1/0-value coverage ; 22           ;
; Total output ports with no 1/0-value coverage       ; 118          ;
; Total output ports with no 1-value coverage         ; 118          ;
; Total output ports with no 0-value coverage         ; 132          ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+----------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                            ;
+----------------------------------+----------------------------------+------------------+
; Node Name                        ; Output Port Name                 ; Output Port Type ;
+----------------------------------+----------------------------------+------------------+
; |dds|f5mhz:inst2|count[1]        ; |dds|f5mhz:inst2|count[1]        ; regout           ;
; |dds|f5mhz:inst2|count[0]        ; |dds|f5mhz:inst2|count[0]        ; regout           ;
; |dds|f5mhz:inst2|count[2]        ; |dds|f5mhz:inst2|count[2]        ; regout           ;
; |dds|receive_f:inst4|qout[10]~29 ; |dds|receive_f:inst4|qout[10]~29 ; combout          ;
; |dds|receive_f:inst4|qout[10]~29 ; |dds|receive_f:inst4|count.11    ; regout           ;
; |dds|receive_f:inst4|count.01    ; |dds|receive_f:inst4|count.01    ; regout           ;
; |dds|receive_f:inst4|qtemp[10]~8 ; |dds|receive_f:inst4|qtemp[10]~8 ; combout          ;
; |dds|receive_f:inst4|qtemp[16]~2 ; |dds|receive_f:inst4|qtemp[16]~2 ; combout          ;
; |dds|receive_f:inst4|qtemp[16]~2 ; |dds|receive_f:inst4|count.10    ; regout           ;
; |dds|receive_f:inst4|count.00    ; |dds|receive_f:inst4|count.00    ; regout           ;
; |dds|receive_f:inst4|qtemp[0]~18 ; |dds|receive_f:inst4|qtemp[0]~18 ; combout          ;
; |dds|clock                       ; |dds|clock                       ; combout          ;
; |dds|mcuclk                      ; |dds|mcuclk                      ; combout          ;
; |dds|fre[2]                      ; |dds|fre[2]                      ; combout          ;
; |dds|fre[3]                      ; |dds|fre[3]                      ; combout          ;
; |dds|fre[4]                      ; |dds|fre[4]                      ; combout          ;
; |dds|fre[5]                      ; |dds|fre[5]                      ; combout          ;
; |dds|fre[6]                      ; |dds|fre[6]                      ; combout          ;
; |dds|fre[7]                      ; |dds|fre[7]                      ; combout          ;
; |dds|fre[0]                      ; |dds|fre[0]                      ; combout          ;
; |dds|fre[1]                      ; |dds|fre[1]                      ; combout          ;
; |dds|wr                          ; |dds|wr                          ; padio            ;
+----------------------------------+----------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                                                                                                              ;
+-------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                                   ; Output Port Name                                                                                                     ; Output Port Type ;
+-------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------+------------------+
; |dds|sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[7]                    ; |dds|sine_rom:inst|altsyncram:altsyncram_component|altsyncram_lu21:auto_generated|q_a[7]                             ; portadataout0    ;