dds.fit.summary

基于飓风1 fpga 和stc单片机的dds信号源 程序是自己些的 能用 最大频率是2M

Fitter Status : Successful - Tue May 22 23:46:29 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : dds
Top-level Entity Name : dds
Family : Cyclone
Device : EP1C3T144C8
Timing Models : Final
Total logic elements : 420 / 2,910 ( 14 % )
Total pins : 26 / 104 ( 25 % )
Total virtual pins : 0
Total memory bits : 26,624 / 59,904 ( 44 % )
Total PLLs : 0 / 1 ( 0 % )