ps2rs232.tan.qmsg

利用FPGA控制PS2

{ "Info" "ITDB_TSU_RESULT" "div_256:inst4\|clk rst mclk 6.527 ns register " "Info: tsu for register \"div_256:inst4\|clk\" (data pin = \"rst\", clock pin = \"mclk\") is 6.527 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.737 ns + Longest pin register " "Info: + Longest pin to register delay is 9.737 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns rst 1 PIN PIN_AA3 43 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_AA3; Fanout = 43; PIN Node = 'rst'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "ps2rs232.bdf" "" { Schematic "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2rs232.bdf" { { -80 -336 -168 -64 "rst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.938 ns) + CELL(0.855 ns) 9.737 ns div_256:inst4\|clk 2 REG LCFF_X27_Y21_N9 1 " "Info: 2: + IC(7.938 ns) + CELL(0.855 ns) = 9.737 ns; Loc. = LCFF_X27_Y21_N9; Fanout = 1; REG Node = 'div_256:inst4\|clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.793 ns" { rst div_256:inst4|clk } "NODE_NAME" } } { "div_256.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/div_256.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.799 ns ( 18.48 % ) " "Info: Total cell delay = 1.799 ns ( 18.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.938 ns ( 81.52 % ) " "Info: Total interconnect delay = 7.938 ns ( 81.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.737 ns" { rst div_256:inst4|clk } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.737 ns" { rst rst~combout div_256:inst4|clk } { 0.000ns 0.000ns 7.938ns } { 0.000ns 0.944ns 0.855ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "div_256.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/div_256.v" 5 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk destination 3.170 ns - Shortest register " "Info: - Shortest clock path from clock \"mclk\" to destination register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.080 ns) 1.080 ns mclk 1 CLK PIN_W12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.080 ns) = 1.080 ns; Loc. = PIN_W12; Fanout = 1; CLK Node = 'mclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { mclk } "NODE_NAME" } } { "ps2rs232.bdf" "" { Schematic "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2rs232.bdf" { { -96 -336 -168 -80 "mclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.232 ns) + CELL(0.000 ns) 1.312 ns mclk~clkctrl 2 COMB CLKCTRL_G14 21 " "Info: 2: + IC(0.232 ns) + CELL(0.000 ns) = 1.312 ns; Loc. = CLKCTRL_G14; Fanout = 21; COMB Node = 'mclk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.232 ns" { mclk mclk~clkctrl } "NODE_NAME" } } { "ps2rs232.bdf" "" { Schematic "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2rs232.bdf" { { -96 -336 -168 -80 "mclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.192 ns) + CELL(0.666 ns) 3.170 ns div_256:inst4\|clk 3 REG LCFF_X27_Y21_N9 1 " "Info: 3: + IC(1.192 ns) + CELL(0.666 ns) = 3.170 ns; Loc. = LCFF_X27_Y21_N9; Fanout = 1; REG Node = 'div_256:inst4\|clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.858 ns" { mclk~clkctrl div_256:inst4|clk } "NODE_NAME" } } { "div_256.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/div_256.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.746 ns ( 55.08 % ) " "Info: Total cell delay = 1.746 ns ( 55.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.424 ns ( 44.92 % ) " "Info: Total interconnect delay = 1.424 ns ( 44.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { mclk mclk~clkctrl div_256:inst4|clk } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { mclk mclk~combout mclk~clkctrl div_256:inst4|clk } { 0.000ns 0.000ns 0.232ns 1.192ns } { 0.000ns 1.080ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.737 ns" { rst div_256:inst4|clk } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.737 ns" { rst rst~combout div_256:inst4|clk } { 0.000ns 0.000ns 7.938ns } { 0.000ns 0.944ns 0.855ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { mclk mclk~clkctrl div_256:inst4|clk } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { mclk mclk~combout mclk~clkctrl div_256:inst4|clk } { 0.000ns 0.000ns 0.232ns 1.192ns } { 0.000ns 1.080ns 0.000ns 0.666ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "mclk ps2_data ps2_keyboard_interface:inst1\|m1_state.m1_tx_rising_edge_marker 17.091 ns register " "Info: tco from clock \"mclk\" to destination pin \"ps2_data\" through register \"ps2_keyboard_interface:inst1\|m1_state.m1_tx_rising_edge_marker\" is 17.091 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk source 7.958 ns + Longest register " "Info: + Longest clock path from clock \"mclk\" to source register is 7.958 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.080 ns) 1.080 ns mclk 1 CLK PIN_W12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.080 ns) = 1.080 ns; Loc. = PIN_W12; Fanout = 1; CLK Node = 'mclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { mclk } "NODE_NAME" } } { "ps2rs232.bdf" "" { Schematic "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2rs232.bdf" { { -96 -336 -168 -80 "mclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.232 ns) + CELL(0.000 ns) 1.312 ns mclk~clkctrl 2 COMB CLKCTRL_G14 21 " "Info: 2: + IC(0.232 ns) + CELL(0.000 ns) = 1.312 ns; Loc. = CLKCTRL_G14; Fanout = 21; COMB Node = 'mclk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.232 ns" { mclk mclk~clkctrl } "NODE_NAME" } } { "ps2rs232.bdf" "" { Schematic "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2rs232.bdf" { { -96 -336 -168 -80 "mclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.192 ns) + CELL(0.970 ns) 3.474 ns div_256:inst4\|clk 3 REG LCFF_X27_Y21_N9 1 " "Info: 3: + IC(1.192 ns) + CELL(0.970 ns) = 3.474 ns; Loc. = LCFF_X27_Y21_N9; Fanout = 1; REG Node = 'div_256:inst4\|clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.162 ns" { mclk~clkctrl div_256:inst4|clk } "NODE_NAME" } } { "div_256.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/div_256.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.616 ns) + CELL(0.000 ns) 6.090 ns div_256:inst4\|clk~clkctrl 4 COMB CLKCTRL_G1 59 " "Info: 4: + IC(2.616 ns) + CELL(0.000 ns) = 6.090 ns; Loc. = CLKCTRL_G1; Fanout = 59; COMB Node = 'div_256:inst4\|clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.616 ns" { div_256:inst4|clk div_256:inst4|clk~clkctrl } "NODE_NAME" } } { "div_256.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/div_256.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.202 ns) + CELL(0.666 ns) 7.958 ns ps2_keyboard_interface:inst1\|m1_state.m1_tx_rising_edge_marker 5 REG LCFF_X27_Y23_N23 4 " "Info: 5: + IC(1.202 ns) + CELL(0.666 ns) = 7.958 ns; Loc. = LCFF_X27_Y23_N23; Fanout = 4; REG Node = 'ps2_keyboard_interface:inst1\|m1_state.m1_tx_rising_edge_marker'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.868 ns" { div_256:inst4|clk~clkctrl ps2_keyboard_interface:inst1|m1_state.m1_tx_rising_edge_marker } "NODE_NAME" } } { "ps2_keyboard_interface.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2_keyboard_interface.v" 229 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.716 ns ( 34.13 % ) " "Info: Total cell delay = 2.716 ns ( 34.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.242 ns ( 65.87 % ) " "Info: Total interconnect delay = 5.242 ns ( 65.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.958 ns" { mclk mclk~clkctrl div_256:inst4|clk div_256:inst4|clk~clkctrl ps2_keyboard_interface:inst1|m1_state.m1_tx_rising_edge_marker } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.958 ns" { mclk mclk~combout mclk~clkctrl div_256:inst4|clk div_256:inst4|clk~clkctrl ps2_keyboard_interface:inst1|m1_state.m1_tx_rising_edge_marker } { 0.000ns 0.000ns 0.232ns 1.192ns 2.616ns 1.202ns } { 0.000ns 1.080ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "ps2_keyboard_interface.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2_keyboard_interface.v" 229 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.829 ns + Longest register pin " "Info: + Longest register to pin delay is 8.829 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ps2_keyboard_interface:inst1\|m1_state.m1_tx_rising_edge_marker 1 REG LCFF_X27_Y23_N23 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y23_N23; Fanout = 4; REG Node = 'ps2_keyboard_interface:inst1\|m1_state.m1_tx_rising_edge_marker'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ps2_keyboard_interface:inst1|m1_state.m1_tx_rising_edge_marker } "NODE_NAME" } } { "ps2_keyboard_interface.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2_keyboard_interface.v" 229 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.186 ns) + CELL(0.539 ns) 1.725 ns ps2_keyboard_interface:inst1\|m1_state.m1_tx_wait_clk_h~30 2 COMB LCCOMB_X27_Y21_N16 1 " "Info: 2: + IC(1.186 ns) + CELL(0.539 ns) = 1.725 ns; Loc. = LCCOMB_X27_Y21_N16; Fanout = 1; COMB Node = 'ps2_keyboard_interface:inst1\|m1_state.m1_tx_wait_clk_h~30'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.725 ns" { ps2_keyboard_interface:inst1|m1_state.m1_tx_rising_edge_marker ps2_keyboard_interface:inst1|m1_state.m1_tx_wait_clk_h~30 } "NODE_NAME" } } { "ps2_keyboard_interface.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2_keyboard_interface.v" 229 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.389 ns) + CELL(0.647 ns) 2.761 ns ps2_keyboard_interface:inst1\|Selector11~28 3 COMB LCCOMB_X27_Y21_N10 1 " "Info: 3: + IC(0.389 ns) + CELL(0.647 ns) = 2.761 ns; Loc. = LCCOMB_X27_Y21_N10; Fanout = 1; COMB Node = 'ps2_keyboard_interface:inst1\|Selector11~28'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.036 ns" { ps2_keyboard_interface:inst1|m1_state.m1_tx_wait_clk_h~30 ps2_keyboard_interface:inst1|Selector11~28 } "NODE_NAME" } } { "ps2_keyboard_interface.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2_keyboard_interface.v" 289 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.012 ns) + CELL(3.056 ns) 8.829 ns ps2_data 4 PIN PIN_E21 0 " "Info: 4: + IC(3.012 ns) + CELL(3.056 ns) = 8.829 ns; Loc. = PIN_E21; Fanout = 0; PIN Node = 'ps2_data'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.068 ns" { ps2_keyboard_interface:inst1|Selector11~28 ps2_data } "NODE_NAME" } } { "ps2rs232.bdf" "" { Schematic "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2rs232.bdf" { { 8 712 888 24 "ps2_data" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.242 ns ( 48.05 % ) " "Info: Total cell delay = 4.242 ns ( 48.05 % )" {  } {  } 0 0