📄 ps2rs232.tan.qmsg

📁 利用FPGA控制PS2
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "mclk register uart_if:inst3\|uart:U1\|txmit:u2\|tbr\[0\] register uart_if:inst3\|uart:U1\|txmit:u2\|tsr\[0\] 103.89 MHz 9.626 ns Internal " "Info: Clock \"mclk\" has Internal fmax of 103.89 MHz between source register \"uart_if:inst3\|uart:U1\|txmit:u2\|tbr\[0\]\" and destination register \"uart_if:inst3\|uart:U1\|txmit:u2\|tsr\[0\]\" (period= 9.626 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.751 ns + Longest register register " "Info: + Longest register to register delay is 0.751 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns uart_if:inst3\|uart:U1\|txmit:u2\|tbr\[0\] 1 REG LCFF_X36_Y16_N7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X36_Y16_N7; Fanout = 1; REG Node = 'uart_if:inst3\|uart:U1\|txmit:u2\|tbr\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { uart_if:inst3|uart:U1|txmit:u2|tbr[0] } "NODE_NAME" } } { "txmit.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/txmit.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.206 ns) 0.643 ns uart_if:inst3\|uart:U1\|txmit:u2\|tsr~833 2 COMB LCCOMB_X36_Y16_N20 1 " "Info: 2: + IC(0.437 ns) + CELL(0.206 ns) = 0.643 ns; Loc. = LCCOMB_X36_Y16_N20; Fanout = 1; COMB Node = 'uart_if:inst3\|uart:U1\|txmit:u2\|tsr~833'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.643 ns" { uart_if:inst3|uart:U1|txmit:u2|tbr[0] uart_if:inst3|uart:U1|txmit:u2|tsr~833 } "NODE_NAME" } } { "txmit.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/txmit.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.751 ns uart_if:inst3\|uart:U1\|txmit:u2\|tsr\[0\] 3 REG LCFF_X36_Y16_N21 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.751 ns; Loc. = LCFF_X36_Y16_N21; Fanout = 2; REG Node = 'uart_if:inst3\|uart:U1\|txmit:u2\|tsr\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { uart_if:inst3|uart:U1|txmit:u2|tsr~833 uart_if:inst3|uart:U1|txmit:u2|tsr[0] } "NODE_NAME" } } { "txmit.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/txmit.v" 92 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.314 ns ( 41.81 % ) " "Info: Total cell delay = 0.314 ns ( 41.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.437 ns ( 58.19 % ) " "Info: Total interconnect delay = 0.437 ns ( 58.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.751 ns" { uart_if:inst3|uart:U1|txmit:u2|tbr[0] uart_if:inst3|uart:U1|txmit:u2|tsr~833 uart_if:inst3|uart:U1|txmit:u2|tsr[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "0.751 ns" { uart_if:inst3|uart:U1|txmit:u2|tbr[0] uart_if:inst3|uart:U1|txmit:u2|tsr~833 uart_if:inst3|uart:U1|txmit:u2|tsr[0] } { 0.000ns 0.437ns 0.000ns } { 0.000ns 0.206ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.798 ns - Smallest " "Info: - Smallest clock skew is -3.798 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk destination 9.992 ns + Shortest register " "Info: + Shortest clock path from clock \"mclk\" to destination register is 9.992 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.080 ns) 1.080 ns mclk 1 CLK PIN_W12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.080 ns) = 1.080 ns; Loc. = PIN_W12; Fanout = 1; CLK Node = 'mclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { mclk } "NODE_NAME" } } { "ps2rs232.bdf" "" { Schematic "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2rs232.bdf" { { -96 -336 -168 -80 "mclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.232 ns) + CELL(0.000 ns) 1.312 ns mclk~clkctrl 2 COMB CLKCTRL_G14 21 " "Info: 2: + IC(0.232 ns) + CELL(0.000 ns) = 1.312 ns; Loc. = CLKCTRL_G14; Fanout = 21; COMB Node = 'mclk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.232 ns" { mclk mclk~clkctrl } "NODE_NAME" } } { "ps2rs232.bdf" "" { Schematic "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2rs232.bdf" { { -96 -336 -168 -80 "mclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.199 ns) + CELL(0.970 ns) 3.481 ns div_4:inst\|acc\[12\] 3 REG LCFF_X1_Y18_N27 1 " "Info: 3: + IC(1.199 ns) + CELL(0.970 ns) = 3.481 ns; Loc. = LCFF_X1_Y18_N27; Fanout = 1; REG Node = 'div_4:inst\|acc\[12\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.169 ns" { mclk~clkctrl div_4:inst|acc[12] } "NODE_NAME" } } { "div_4.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/div_4.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.806 ns) + CELL(0.000 ns) 4.287 ns div_4:inst\|acc\[12\]~clkctrl 4 COMB CLKCTRL_G0 31 " "Info: 4: + IC(0.806 ns) + CELL(0.000 ns) = 4.287 ns; Loc. = CLKCTRL_G0; Fanout = 31; COMB Node = 'div_4:inst\|acc\[12\]~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.806 ns" { div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl } "NODE_NAME" } } { "div_4.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/div_4.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.178 ns) + CELL(0.970 ns) 6.435 ns uart_if:inst3\|uart:U1\|txmit:u2\|clkdiv\[3\] 5 REG LCFF_X35_Y14_N21 2 " "Info: 5: + IC(1.178 ns) + CELL(0.970 ns) = 6.435 ns; Loc. = LCFF_X35_Y14_N21; Fanout = 2; REG Node = 'uart_if:inst3\|uart:U1\|txmit:u2\|clkdiv\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.148 ns" { div_4:inst|acc[12]~clkctrl uart_if:inst3|uart:U1|txmit:u2|clkdiv[3] } "NODE_NAME" } } { "txmit.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/txmit.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.703 ns) + CELL(0.000 ns) 8.138 ns uart_if:inst3\|uart:U1\|txmit:u2\|clkdiv\[3\]~clkctrl 6 COMB CLKCTRL_G15 14 " "Info: 6: + IC(1.703 ns) + CELL(0.000 ns) = 8.138 ns; Loc. = CLKCTRL_G15; Fanout = 14; COMB Node = 'uart_if:inst3\|uart:U1\|txmit:u2\|clkdiv\[3\]~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.703 ns" { uart_if:inst3|uart:U1|txmit:u2|clkdiv[3] uart_if:inst3|uart:U1|txmit:u2|clkdiv[3]~clkctrl } "NODE_NAME" } } { "txmit.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/txmit.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.188 ns) + CELL(0.666 ns) 9.992 ns uart_if:inst3\|uart:U1\|txmit:u2\|tsr\[0\] 7 REG LCFF_X36_Y16_N21 2 " "Info: 7: + IC(1.188 ns) + CELL(0.666 ns) = 9.992 ns; Loc. = LCFF_X36_Y16_N21; Fanout = 2; REG Node = 'uart_if:inst3\|uart:U1\|txmit:u2\|tsr\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.854 ns" { uart_if:inst3|uart:U1|txmit:u2|clkdiv[3]~clkctrl uart_if:inst3|uart:U1|txmit:u2|tsr[0] } "NODE_NAME" } } { "txmit.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/txmit.v" 92 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.686 ns ( 36.89 % ) " "Info: Total cell delay = 3.686 ns ( 36.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.306 ns ( 63.11 % ) " "Info: Total interconnect delay = 6.306 ns ( 63.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.992 ns" { mclk mclk~clkctrl div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl uart_if:inst3|uart:U1|txmit:u2|clkdiv[3] uart_if:inst3|uart:U1|txmit:u2|clkdiv[3]~clkctrl uart_if:inst3|uart:U1|txmit:u2|tsr[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.992 ns" { mclk mclk~combout mclk~clkctrl div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl uart_if:inst3|uart:U1|txmit:u2|clkdiv[3] uart_if:inst3|uart:U1|txmit:u2|clkdiv[3]~clkctrl uart_if:inst3|uart:U1|txmit:u2|tsr[0] } { 0.000ns 0.000ns 0.232ns 1.199ns 0.806ns 1.178ns 1.703ns 1.188ns } { 0.000ns 1.080ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk source 13.790 ns - Longest register " "Info: - Longest clock path from clock \"mclk\" to source register is 13.790 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.080 ns) 1.080 ns mclk 1 CLK PIN_W12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.080 ns) = 1.080 ns; Loc. = PIN_W12; Fanout = 1; CLK Node = 'mclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { mclk } "NODE_NAME" } } { "ps2rs232.bdf" "" { Schematic "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2rs232.bdf" { { -96 -336 -168 -80 "mclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.232 ns) + CELL(0.000 ns) 1.312 ns mclk~clkctrl 2 COMB CLKCTRL_G14 21 " "Info: 2: + IC(0.232 ns) + CELL(0.000 ns) = 1.312 ns; Loc. = CLKCTRL_G14; Fanout = 21; COMB Node = 'mclk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.232 ns" { mclk mclk~clkctrl } "NODE_NAME" } } { "ps2rs232.bdf" "" { Schematic "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2rs232.bdf" { { -96 -336 -168 -80 "mclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.199 ns) + CELL(0.970 ns) 3.481 ns div_4:inst\|acc\[12\] 3 REG LCFF_X1_Y18_N27 1 " "Info: 3: + IC(1.199 ns) + CELL(0.970 ns) = 3.481 ns; Loc. = LCFF_X1_Y18_N27; Fanout = 1; REG Node = 'div_4:inst\|acc\[12\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.169 ns" { mclk~clkctrl div_4:inst|acc[12] } "NODE_NAME" } } { "div_4.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/div_4.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.806 ns) + CELL(0.000 ns) 4.287 ns div_4:inst\|acc\[12\]~clkctrl 4 COMB CLKCTRL_G0 31 " "Info: 4: + IC(0.806 ns) + CELL(0.000 ns) = 4.287 ns; Loc. = CLKCTRL_G0; Fanout = 31; COMB Node = 'div_4:inst\|acc\[12\]~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.806 ns" { div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl } "NODE_NAME" } } { "div_4.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/div_4.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.199 ns) + CELL(0.970 ns) 6.456 ns uart_if:inst3\|cnt\[3\] 5 REG LCFF_X2_Y18_N17 2 " "Info: 5: + IC(1.199 ns) + CELL(0.970 ns) = 6.456 ns; Loc. = LCFF_X2_Y18_N17; Fanout = 2; REG Node = 'uart_if:inst3\|cnt\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.169 ns" { div_4:inst|acc[12]~clkctrl uart_if:inst3|cnt[3] } "NODE_NAME" } } { "uart_if.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/uart_if.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.112 ns) + CELL(0.000 ns) 7.568 ns uart_if:inst3\|cnt\[3\]~clkctrl 6 COMB CLKCTRL_G2 29 " "Info: 6: + IC(1.112 ns) + CELL(0.000 ns) = 7.568 ns; Loc. = CLKCTRL_G2; Fanout = 29; COMB Node = 'uart_if:inst3\|cnt\[3\]~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.112 ns" { uart_if:inst3|cnt[3] uart_if:inst3|cnt[3]~clkctrl } "NODE_NAME" } } { "uart_if.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/uart_if.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.182 ns) + CELL(0.970 ns) 9.720 ns uart_if:inst3\|wrn 7 REG LCFF_X36_Y15_N1 2 " "Info: 7: + IC(1.182 ns) + CELL(0.970 ns) = 9.720 ns; Loc. = LCFF_X36_Y15_N1; Fanout = 2; REG Node = 'uart_if:inst3\|wrn'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.152 ns" { uart_if:inst3|cnt[3]~clkctrl uart_if:inst3|wrn } "NODE_NAME" } } { "uart_if.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/uart_if.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.213 ns) + CELL(0.000 ns) 11.933 ns uart_if:inst3\|wrn~clkctrl 8 COMB CLKCTRL_G5 7 " "Info: 8: + IC(2.213 ns) + CELL(0.000 ns) = 11.933 ns; Loc. = CLKCTRL_G5; Fanout = 7; COMB Node = 'uart_if:inst3\|wrn~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.213 ns" { uart_if:inst3|wrn uart_if:inst3|wrn~clkctrl } "NODE_NAME" } } { "uart_if.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/uart_if.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.191 ns) + CELL(0.666 ns) 13.790 ns uart_if:inst3\|uart:U1\|txmit:u2\|tbr\[0\] 9 REG LCFF_X36_Y16_N7 1 " "Info: 9: + IC(1.191 ns) + CELL(0.666 ns) = 13.790 ns; Loc. = LCFF_X36_Y16_N7; Fanout = 1; REG Node = 'uart_if:inst3\|uart:U1\|txmit:u2\|tbr\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.857 ns" { uart_if:inst3|wrn~clkctrl uart_if:inst3|uart:U1|txmit:u2|tbr[0] } "NODE_NAME" } } { "txmit.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/txmit.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.656 ns ( 33.76 % ) " "Info: Total cell delay = 4.656 ns ( 33.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.134 ns ( 66.24 % ) " "Info: Total interconnect delay = 9.134 ns ( 66.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.790 ns" { mclk mclk~clkctrl div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl uart_if:inst3|cnt[3] uart_if:inst3|cnt[3]~clkctrl uart_if:inst3|wrn uart_if:inst3|wrn~clkctrl uart_if:inst3|uart:U1|txmit:u2|tbr[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "13.790 ns" { mclk mclk~combout mclk~clkctrl div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl uart_if:inst3|cnt[3] uart_if:inst3|cnt[3]~clkctrl uart_if:inst3|wrn uart_if:inst3|wrn~clkctrl uart_if:inst3|uart:U1|txmit:u2|tbr[0] } { 0.000ns 0.000ns 0.232ns 1.199ns 0.806ns 1.199ns 1.112ns 1.182ns 2.213ns 1.191ns } { 0.000ns 1.080ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.992 ns" { mclk mclk~clkctrl div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl uart_if:inst3|uart:U1|txmit:u2|clkdiv[3] uart_if:inst3|uart:U1|txmit:u2|clkdiv[3]~clkctrl uart_if:inst3|uart:U1|txmit:u2|tsr[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.992 ns" { mclk mclk~combout mclk~clkctrl div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl uart_if:inst3|uart:U1|txmit:u2|clkdiv[3] uart_if:inst3|uart:U1|txmit:u2|clkdiv[3]~clkctrl uart_if:inst3|uart:U1|txmit:u2|tsr[0] } { 0.000ns 0.000ns 0.232ns 1.199ns 0.806ns 1.178ns 1.703ns 1.188ns } { 0.000ns 1.080ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.790 ns" { mclk mclk~clkctrl div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl uart_if:inst3|cnt[3] uart_if:inst3|cnt[3]~clkctrl uart_if:inst3|wrn uart_if:inst3|wrn~clkctrl uart_if:inst3|uart:U1|txmit:u2|tbr[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "13.790 ns" { mclk mclk~combout mclk~clkctrl div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl uart_if:inst3|cnt[3] uart_if:inst3|cnt[3]~clkctrl uart_if:inst3|wrn uart_if:inst3|wrn~clkctrl uart_if:inst3|uart:U1|txmit:u2|tbr[0] } { 0.000ns 0.000ns 0.232ns 1.199ns 0.806ns 1.199ns 1.112ns 1.182ns 2.213ns 1.191ns } { 0.000ns 1.080ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "txmit.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/txmit.v" 75 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "txmit.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/txmit.v" 92 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "txmit.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/txmit.v" 75 -1 0 } } { "txmit.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/txmit.v" 92 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.751 ns" { uart_if:inst3|uart:U1|txmit:u2|tbr[0] uart_if:inst3|uart:U1|txmit:u2|tsr~833 uart_if:inst3|uart:U1|txmit:u2|tsr[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "0.751 ns" { uart_if:inst3|uart:U1|txmit:u2|tbr[0] uart_if:inst3|uart:U1|txmit:u2|tsr~833 uart_if:inst3|uart:U1|txmit:u2|tsr[0] } { 0.000ns 0.437ns 0.000ns } { 0.000ns 0.206ns 0.108ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.992 ns" { mclk mclk~clkctrl div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl uart_if:inst3|uart:U1|txmit:u2|clkdiv[3] uart_if:inst3|uart:U1|txmit:u2|clkdiv[3]~clkctrl uart_if:inst3|uart:U1|txmit:u2|tsr[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.992 ns" { mclk mclk~combout mclk~clkctrl div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl uart_if:inst3|uart:U1|txmit:u2|clkdiv[3] uart_if:inst3|uart:U1|txmit:u2|clkdiv[3]~clkctrl uart_if:inst3|uart:U1|txmit:u2|tsr[0] } { 0.000ns 0.000ns 0.232ns 1.199ns 0.806ns 1.178ns 1.703ns 1.188ns } { 0.000ns 1.080ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.790 ns" { mclk mclk~clkctrl div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl uart_if:inst3|cnt[3] uart_if:inst3|cnt[3]~clkctrl uart_if:inst3|wrn uart_if:inst3|wrn~clkctrl uart_if:inst3|uart:U1|txmit:u2|tbr[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "13.790 ns" { mclk mclk~combout mclk~clkctrl div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl uart_if:inst3|cnt[3] uart_if:inst3|cnt[3]~clkctrl uart_if:inst3|wrn uart_if:inst3|wrn~clkctrl uart_if:inst3|uart:U1|txmit:u2|tbr[0] } { 0.000ns 0.000ns 0.232ns 1.199ns 0.806ns 1.199ns 1.112ns 1.182ns 2.213ns 1.191ns } { 0.000ns 1.080ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "mclk 42 " "Warning: Circuit may not operate. Detected 42 non-operational path(s) clocked by clock \"mclk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "uart_if:inst3\|din\[3\] uart_if:inst3\|uart:U1\|txmit:u2\|tbr\[3\] mclk 3.0 ns " "Info: Found hold time violation between source  pin or register \"uart_if:inst3\|din\[3\]\" and destination pin or register \"uart_if:inst3\|uart:U1\|txmit:u2\|tbr\[3\]\" for clock \"mclk\" (Hold time is 3.0 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.372 ns + Largest " "Info: + Largest clock skew is 4.372 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk destination 13.790 ns + Longest register " "Info: + Longest clock path from clock \"mclk\" to destination register is 13.790 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.080 ns) 1.080 ns mclk 1 CLK PIN_W12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.080 ns) = 1.080 ns; Loc. = PIN_W12; Fanout = 1; CLK Node = 'mclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { mclk } "NODE_NAME" } } { "ps2rs232.bdf" "" { Schematic "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2rs232.bdf" { { -96 -336 -168 -80 "mclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.232 ns) + CELL(0.000 ns) 1.312 ns mclk~clkctrl 2 COMB CLKCTRL_G14 21 " "Info: 2: + IC(0.232 ns) + CELL(0.000 ns) = 1.312 ns; Loc. = CLKCTRL_G14; Fanout = 21; COMB Node = 'mclk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.232 ns" { mclk mclk~clkctrl } "NODE_NAME" } } { "ps2rs232.bdf" "" { Schematic "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2rs232.bdf" { { -96 -336 -168 -80 "mclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.199 ns) + CELL(0.970 ns) 3.481 ns div_4:inst\|acc\[12\] 3 REG LCFF_X1_Y18_N27 1 " "Info: 3: + IC(1.199 ns) + CELL(0.970 ns) = 3.481 ns; Loc. = LCFF_X1_Y18_N27; Fanout = 1; REG Node = 'div_4:inst\|acc\[12\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.169 ns" { mclk~clkctrl div_4:inst|acc[12] } "NODE_NAME" } } { "div_4.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/div_4.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.806 ns) + CELL(0.000 ns) 4.287 ns div_4:inst\|acc\[12\]~clkctrl 4 COMB CLKCTRL_G0 31 " "Info: 4: + IC(0.806 ns) + CELL(0.000 ns) = 4.287 ns; Loc. = CLKCTRL_G0; Fanout = 31; COMB Node = 'div_4:inst\|acc\[12\]~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.806 ns" { div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl } "NODE_NAME" } } { "div_4.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/div_4.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.199 ns) + CELL(0.970 ns) 6.456 ns uart_if:inst3\|cnt\[3\] 5 REG LCFF_X2_Y18_N17 2 " "Info: 5: + IC(1.199 ns) + CELL(0.970 ns) = 6.456 ns; Loc. = LCFF_X2_Y18_N17; Fanout = 2; REG Node = 'uart_if:inst3\|cnt\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.169 ns" { div_4:inst|acc[12]~clkctrl uart_if:inst3|cnt[3] } "NODE_NAME" } } { "uart_if.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/uart_if.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.112 ns) + CELL(0.000 ns) 7.568 ns uart_if:inst3\|cnt\[3\]~clkctrl 6 COMB CLKCTRL_G2 29 " "Info: 6: + IC(1.112 ns) + CELL(0.000 ns) = 7.568 ns; Loc. = CLKCTRL_G2; Fanout = 29; COMB Node = 'uart_if:inst3\|cnt\[3\]~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.112 ns" { uart_if:inst3|cnt[3] uart_if:inst3|cnt[3]~clkctrl } "NODE_NAME" } } { "uart_if.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/uart_if.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.182 ns) + CELL(0.970 ns) 9.720 ns uart_if:inst3\|wrn 7 REG LCFF_X36_Y15_N1 2 " "Info: 7: + IC(1.182 ns) + CELL(0.970 ns) = 9.720 ns; Loc. = LCFF_X36_Y15_N1; Fanout = 2; REG Node = 'uart_if:inst3\|wrn'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.152 ns" { uart_if:inst3|cnt[3]~clkctrl uart_if:inst3|wrn } "NODE_NAME" } } { "uart_if.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/uart_if.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.213 ns) + CELL(0.000 ns) 11.933 ns uart_if:inst3\|wrn~clkctrl 8 COMB CLKCTRL_G5 7 " "Info: 8: + IC(2.213 ns) + CELL(0.000 ns) = 11.933 ns; Loc. = CLKCTRL_G5; Fanout = 7; COMB Node = 'uart_if:inst3\|wrn~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.213 ns" { uart_if:inst3|wrn uart_if:inst3|wrn~clkctrl } "NODE_NAME" } } { "uart_if.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/uart_if.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.191 ns) + CELL(0.666 ns) 13.790 ns uart_if:inst3\|uart:U1\|txmit:u2\|tbr\[3\] 9 REG LCFF_X36_Y16_N23 1 " "Info: 9: + IC(1.191 ns) + CELL(0.666 ns) = 13.790 ns; Loc. = LCFF_X36_Y16_N23; Fanout = 1; REG Node = 'uart_if:inst3\|uart:U1\|txmit:u2\|tbr\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.857 ns" { uart_if:inst3|wrn~clkctrl uart_if:inst3|uart:U1|txmit:u2|tbr[3] } "NODE_NAME" } } { "txmit.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/txmit.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.656 ns ( 33.76 % ) " "Info: Total cell delay = 4.656 ns ( 33.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.134 ns ( 66.24 % ) " "Info: Total interconnect delay = 9.134 ns ( 66.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.790 ns" { mclk mclk~clkctrl div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl uart_if:inst3|cnt[3] uart_if:inst3|cnt[3]~clkctrl uart_if:inst3|wrn uart_if:inst3|wrn~clkctrl uart_if:inst3|uart:U1|txmit:u2|tbr[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "13.790 ns" { mclk mclk~combout mclk~clkctrl div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl uart_if:inst3|cnt[3] uart_if:inst3|cnt[3]~clkctrl uart_if:inst3|wrn uart_if:inst3|wrn~clkctrl uart_if:inst3|uart:U1|txmit:u2|tbr[3] } { 0.000ns 0.000ns 0.232ns 1.199ns 0.806ns 1.199ns 1.112ns 1.182ns 2.213ns 1.191ns } { 0.000ns 1.080ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk source 9.418 ns - Shortest register " "Info: - Shortest clock path from clock \"mclk\" to source register is 9.418 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.080 ns) 1.080 ns mclk 1 CLK PIN_W12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.080 ns) = 1.080 ns; Loc. = PIN_W12; Fanout = 1; CLK Node = 'mclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { mclk } "NODE_NAME" } } { "ps2rs232.bdf" "" { Schematic "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2rs232.bdf" { { -96 -336 -168 -80 "mclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.232 ns) + CELL(0.000 ns) 1.312 ns mclk~clkctrl 2 COMB CLKCTRL_G14 21 " "Info: 2: + IC(0.232 ns) + CELL(0.000 ns) = 1.312 ns; Loc. = CLKCTRL_G14; Fanout = 21; COMB Node = 'mclk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.232 ns" { mclk mclk~clkctrl } "NODE_NAME" } } { "ps2rs232.bdf" "" { Schematic "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2rs232.bdf" { { -96 -336 -168 -80 "mclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.199 ns) + CELL(0.970 ns) 3.481 ns div_4:inst\|acc\[12\] 3 REG LCFF_X1_Y18_N27 1 " "Info: 3: + IC(1.199 ns) + CELL(0.970 ns) = 3.481 ns; Loc. = LCFF_X1_Y18_N27; Fanout = 1; REG Node = 'div_4:inst\|acc\[12\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.169 ns" { mclk~clkctrl div_4:inst|acc[12] } "NODE_NAME" } } { "div_4.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/div_4.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.806 ns) + CELL(0.000 ns) 4.287 ns div_4:inst\|acc\[12\]~clkctrl 4 COMB CLKCTRL_G0 31 " "Info: 4: + IC(0.806 ns) + CELL(0.000 ns) = 4.287 ns; Loc. = CLKCTRL_G0; Fanout = 31; COMB Node = 'div_4:inst\|acc\[12\]~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.806 ns" { div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl } "NODE_NAME" } } { "div_4.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/div_4.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.199 ns) + CELL(0.970 ns) 6.456 ns uart_if:inst3\|cnt\[3\] 5 REG LCFF_X2_Y18_N17 2 " "Info: 5: + IC(1.199 ns) + CELL(0.970 ns) = 6.456 ns; Loc. = LCFF_X2_Y18_N17; Fanout = 2; REG Node = 'uart_if:inst3\|cnt\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.169 ns" { div_4:inst|acc[12]~clkctrl uart_if:inst3|cnt[3] } "NODE_NAME" } } { "uart_if.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/uart_if.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.112 ns) + CELL(0.000 ns) 7.568 ns uart_if:inst3\|cnt\[3\]~clkctrl 6 COMB CLKCTRL_G2 29 " "Info: 6: + IC(1.112 ns) + CELL(0.000 ns) = 7.568 ns; Loc. = CLKCTRL_G2; Fanout = 29; COMB Node = 'uart_if:inst3\|cnt\[3\]~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.112 ns" { uart_if:inst3|cnt[3] uart_if:inst3|cnt[3]~clkctrl } "NODE_NAME" } } { "uart_if.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/uart_if.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.184 ns) + CELL(0.666 ns) 9.418 ns uart_if:inst3\|din\[3\] 7 REG LCFF_X37_Y15_N1 1 " "Info: 7: + IC(1.184 ns) + CELL(0.666 ns) = 9.418 ns; Loc. = LCFF_X37_Y15_N1; Fanout = 1; REG Node = 'uart_if:inst3\|din\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.850 ns" { uart_if:inst3|cnt[3]~clkctrl uart_if:inst3|din[3] } "NODE_NAME" } } { "uart_if.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/uart_if.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.686 ns ( 39.14 % ) " "Info: Total cell delay = 3.686 ns ( 39.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.732 ns ( 60.86 % ) " "Info: Total interconnect delay = 5.732 ns ( 60.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.418 ns" { mclk mclk~clkctrl div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl uart_if:inst3|cnt[3] uart_if:inst3|cnt[3]~clkctrl uart_if:inst3|din[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.418 ns" { mclk mclk~combout mclk~clkctrl div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl uart_if:inst3|cnt[3] uart_if:inst3|cnt[3]~clkctrl uart_if:inst3|din[3] } { 0.000ns 0.000ns 0.232ns 1.199ns 0.806ns 1.199ns 1.112ns 1.184ns } { 0.000ns 1.080ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.790 ns" { mclk mclk~clkctrl div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl uart_if:inst3|cnt[3] uart_if:inst3|cnt[3]~clkctrl uart_if:inst3|wrn uart_if:inst3|wrn~clkctrl uart_if:inst3|uart:U1|txmit:u2|tbr[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "13.790 ns" { mclk mclk~combout mclk~clkctrl div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl uart_if:inst3|cnt[3] uart_if:inst3|cnt[3]~clkctrl uart_if:inst3|wrn uart_if:inst3|wrn~clkctrl uart_if:inst3|uart:U1|txmit:u2|tbr[3] } { 0.000ns 0.000ns 0.232ns 1.199ns 0.806ns 1.199ns 1.112ns 1.182ns 2.213ns 1.191ns } { 0.000ns 1.080ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.418 ns" { mclk mclk~clkctrl div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl uart_if:inst3|cnt[3] uart_if:inst3|cnt[3]~clkctrl uart_if:inst3|din[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.418 ns" { mclk mclk~combout mclk~clkctrl div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl uart_if:inst3|cnt[3] uart_if:inst3|cnt[3]~clkctrl uart_if:inst3|din[3] } { 0.000ns 0.000ns 0.232ns 1.199ns 0.806ns 1.199ns 1.112ns 1.184ns } { 0.000ns 1.080ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "uart_if.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/uart_if.v" 59 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.374 ns - Shortest register register " "Info: - Shortest register to register delay is 1.374 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns uart_if:inst3\|din\[3\] 1 REG LCFF_X37_Y15_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X37_Y15_N1; Fanout = 1; REG Node = 'uart_if:inst3\|din\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { uart_if:inst3|din[3] } "NODE_NAME" } } { "uart_if.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/uart_if.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.060 ns) + CELL(0.206 ns) 1.266 ns uart_if:inst3\|uart:U1\|txmit:u2\|tbr\[3\]~feeder 2 COMB LCCOMB_X36_Y16_N22 1 " "Info: 2: + IC(1.060 ns) + CELL(0.206 ns) = 1.266 ns; Loc. = LCCOMB_X36_Y16_N22; Fanout = 1; COMB Node = 'uart_if:inst3\|uart:U1\|txmit:u2\|tbr\[3\]~feeder'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.266 ns" { uart_if:inst3|din[3] uart_if:inst3|uart:U1|txmit:u2|tbr[3]~feeder } "NODE_NAME" } } { "txmit.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/txmit.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.374 ns uart_if:inst3\|uart:U1\|txmit:u2\|tbr\[3\] 3 REG LCFF_X36_Y16_N23 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.374 ns; Loc. = LCFF_X36_Y16_N23; Fanout = 1; REG Node = 'uart_if:inst3\|uart:U1\|txmit:u2\|tbr\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { uart_if:inst3|uart:U1|txmit:u2|tbr[3]~feeder uart_if:inst3|uart:U1|txmit:u2|tbr[3] } "NODE_NAME" } } { "txmit.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/txmit.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.314 ns ( 22.85 % ) " "Info: Total cell delay = 0.314 ns ( 22.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.060 ns ( 77.15 % ) " "Info: Total interconnect delay = 1.060 ns ( 77.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.374 ns" { uart_if:inst3|din[3] uart_if:inst3|uart:U1|txmit:u2|tbr[3]~feeder uart_if:inst3|uart:U1|txmit:u2|tbr[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.374 ns" { uart_if:inst3|din[3] uart_if:inst3|uart:U1|txmit:u2|tbr[3]~feeder uart_if:inst3|uart:U1|txmit:u2|tbr[3] } { 0.000ns 1.060ns 0.000ns } { 0.000ns 0.206ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "txmit.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/txmit.v" 75 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.790 ns" { mclk mclk~clkctrl div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl uart_if:inst3|cnt[3] uart_if:inst3|cnt[3]~clkctrl uart_if:inst3|wrn uart_if:inst3|wrn~clkctrl uart_if:inst3|uart:U1|txmit:u2|tbr[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "13.790 ns" { mclk mclk~combout mclk~clkctrl div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl uart_if:inst3|cnt[3] uart_if:inst3|cnt[3]~clkctrl uart_if:inst3|wrn uart_if:inst3|wrn~clkctrl uart_if:inst3|uart:U1|txmit:u2|tbr[3] } { 0.000ns 0.000ns 0.232ns 1.199ns 0.806ns 1.199ns 1.112ns 1.182ns 2.213ns 1.191ns } { 0.000ns 1.080ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.418 ns" { mclk mclk~clkctrl div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl uart_if:inst3|cnt[3] uart_if:inst3|cnt[3]~clkctrl uart_if:inst3|din[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.418 ns" { mclk mclk~combout mclk~clkctrl div_4:inst|acc[12] div_4:inst|acc[12]~clkctrl uart_if:inst3|cnt[3] uart_if:inst3|cnt[3]~clkctrl uart_if:inst3|din[3] } { 0.000ns 0.000ns 0.232ns 1.199ns 0.806ns 1.199ns 1.112ns 1.184ns } { 0.000ns 1.080ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.374 ns" { uart_if:inst3|din[3] uart_if:inst3|uart:U1|txmit:u2|tbr[3]~feeder uart_if:inst3|uart:U1|txmit:u2|tbr[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.374 ns" { uart_if:inst3|din[3] uart_if:inst3|uart:U1|txmit:u2|tbr[3]~feeder uart_if:inst3|uart:U1|txmit:u2|tbr[3] } { 0.000ns 1.060ns 0.000ns } { 0.000ns 0.206ns 0.108ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
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