ps2rs232.tan.qmsg

利用FPGA控制PS2

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "data_buf:inst5\|data_in_buf\[0\]~349 " "Warning: Node \"data_buf:inst5\|data_in_buf\[0\]~349\" is a latch" {  } { { "data_buf.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/data_buf.v" 11 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "data_buf:inst5\|data_in_buf\[1\]~360 " "Warning: Node \"data_buf:inst5\|data_in_buf\[1\]~360\" is a latch" {  } { { "data_buf.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/data_buf.v" 11 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "data_buf:inst5\|data_in_buf\[2\]~371 " "Warning: Node \"data_buf:inst5\|data_in_buf\[2\]~371\" is a latch" {  } { { "data_buf.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/data_buf.v" 11 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "data_buf:inst5\|data_in_buf\[3\]~382 " "Warning: Node \"data_buf:inst5\|data_in_buf\[3\]~382\" is a latch" {  } { { "data_buf.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/data_buf.v" 11 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "data_buf:inst5\|data_in_buf\[4\]~393 " "Warning: Node \"data_buf:inst5\|data_in_buf\[4\]~393\" is a latch" {  } { { "data_buf.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/data_buf.v" 11 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "data_buf:inst5\|data_in_buf\[5\]~404 " "Warning: Node \"data_buf:inst5\|data_in_buf\[5\]~404\" is a latch" {  } { { "data_buf.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/data_buf.v" 11 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "data_buf:inst5\|data_in_buf\[6\]~415 " "Warning: Node \"data_buf:inst5\|data_in_buf\[6\]~415\" is a latch" {  } { { "data_buf.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/data_buf.v" 11 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "mclk " "Info: Assuming node \"mclk\" is an undefined clock" {  } { { "ps2rs232.bdf" "" { Schematic "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2rs232.bdf" { { -96 -336 -168 -80 "mclk" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "mclk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "7 " "Warning: Found 7 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "uart_if:inst3\|uart:U1\|rcvr:u1\|clkdiv\[3\] " "Info: Detected ripple clock \"uart_if:inst3\|uart:U1\|rcvr:u1\|clkdiv\[3\]\" as buffer" {  } { { "rcvr.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/rcvr.v" 37 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "uart_if:inst3\|uart:U1\|rcvr:u1\|clkdiv\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "uart_if:inst3\|cnt\[3\] " "Info: Detected ripple clock \"uart_if:inst3\|cnt\[3\]\" as buffer" {  } { { "uart_if.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/uart_if.v" 27 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "uart_if:inst3\|cnt\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "uart_if:inst3\|wrn " "Info: Detected ripple clock \"uart_if:inst3\|wrn\" as buffer" {  } { { "uart_if.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/uart_if.v" 17 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "uart_if:inst3\|wrn" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "div_256:inst4\|clk " "Info: Detected ripple clock \"div_256:inst4\|clk\" as buffer" {  } { { "div_256.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/div_256.v" 5 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "div_256:inst4\|clk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "div_4:inst\|acc\[12\] " "Info: Detected ripple clock \"div_4:inst\|acc\[12\]\" as buffer" {  } { { "div_4.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/div_4.v" 8 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "div_4:inst\|acc\[12\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ps2_keyboard_interface:inst1\|rx_released " "Info: Detected ripple clock \"ps2_keyboard_interface:inst1\|rx_released\" as buffer" {  } { { "ps2_keyboard_interface.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2_keyboard_interface.v" 188 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ps2_keyboard_interface:inst1\|rx_released" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "uart_if:inst3\|uart:U1\|txmit:u2\|clkdiv\[3\] " "Info: Detected ripple clock \"uart_if:inst3\|uart:U1\|txmit:u2\|clkdiv\[3\]\" as buffer" {  } { { "txmit.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/txmit.v" 31 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "uart_if:inst3\|uart:U1\|txmit:u2\|clkdiv\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}