ps2rs232.fit.qmsg

利用FPGA控制PS2

{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "2 unused 3.30 1 1 0 " "Info: Number of I/O pins in group: 2 (unused VREF, 3.30 VCCIO, 1 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 0 46 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 2 37 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  37 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.30V 5 34 " "Info: I/O bank number 3 does not use VREF pins and has 3.30V VCCIO pins. 5 total pin(s) used --  34 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.30V 4 32 " "Info: I/O bank number 4 does not use VREF pins and has 3.30V VCCIO pins. 4 total pin(s) used --  32 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use 3.30V 2 42 " "Info: I/O bank number 5 does not use VREF pins and has 3.30V VCCIO pins. 2 total pin(s) used --  42 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use unused 1 42 " "Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  42 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use unused 1 35 " "Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  35 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use unused 1 38 " "Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  38 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "9.752 ns register register " "Info: Estimated most critical path is register to register delay of 9.752 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ps2_keyboard_interface:inst1\|q\[8\] 1 REG LAB_X29_Y23 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X29_Y23; Fanout = 10; REG Node = 'ps2_keyboard_interface:inst1\|q\[8\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ps2_keyboard_interface:inst1|q[8] } "NODE_NAME" } } { "ps2_keyboard_interface.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2_keyboard_interface.v" 477 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.222 ns) + CELL(0.370 ns) 1.592 ns ps2_keyboard_interface:inst1\|always10~34 2 COMB LAB_X28_Y22 4 " "Info: 2: + IC(1.222 ns) + CELL(0.370 ns) = 1.592 ns; Loc. = LAB_X28_Y22; Fanout = 4; COMB Node = 'ps2_keyboard_interface:inst1\|always10~34'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.592 ns" { ps2_keyboard_interface:inst1|q[8] ps2_keyboard_interface:inst1|always10~34 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.442 ns) + CELL(0.370 ns) 2.404 ns ps2_keyboard_interface:inst1\|Equal71~6126 3 COMB LAB_X28_Y22 10 " "Info: 3: + IC(0.442 ns) + CELL(0.370 ns) = 2.404 ns; Loc. = LAB_X28_Y22; Fanout = 10; COMB Node = 'ps2_keyboard_interface:inst1\|Equal71~6126'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.812 ns" { ps2_keyboard_interface:inst1|always10~34 ps2_keyboard_interface:inst1|Equal71~6126 } "NODE_NAME" } } { "ps2_keyboard_interface.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2_keyboard_interface.v" 655 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.304 ns) + CELL(0.206 ns) 3.914 ns ps2_keyboard_interface:inst1\|Equal71~6178 4 COMB LAB_X30_Y22 2 " "Info: 4: + IC(1.304 ns) + CELL(0.206 ns) = 3.914 ns; Loc. = LAB_X30_Y22; Fanout = 2; COMB Node = 'ps2_keyboard_interface:inst1\|Equal71~6178'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.510 ns" { ps2_keyboard_interface:inst1|Equal71~6126 ps2_keyboard_interface:inst1|Equal71~6178 } "NODE_NAME" } } { "ps2_keyboard_interface.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2_keyboard_interface.v" 655 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.494 ns) + CELL(0.539 ns) 4.947 ns ps2_keyboard_interface:inst1\|WideOr17~211 5 COMB LAB_X29_Y22 1 " "Info: 5: + IC(0.494 ns) + CELL(0.539 ns) = 4.947 ns; Loc. = LAB_X29_Y22; Fanout = 1; COMB Node = 'ps2_keyboard_interface:inst1\|WideOr17~211'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.033 ns" { ps2_keyboard_interface:inst1|Equal71~6178 ps2_keyboard_interface:inst1|WideOr17~211 } "NODE_NAME" } } { "ps2_keyboard_interface.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2_keyboard_interface.v" 586 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.898 ns) + CELL(0.623 ns) 6.468 ns ps2_keyboard_interface:inst1\|WideOr17~212 6 COMB LAB_X29_Y21 2 " "Info: 6: + IC(0.898 ns) + CELL(0.623 ns) = 6.468 ns; Loc. = LAB_X29_Y21; Fanout = 2; COMB Node = 'ps2_keyboard_interface:inst1\|WideOr17~212'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.521 ns" { ps2_keyboard_interface:inst1|WideOr17~211 ps2_keyboard_interface:inst1|WideOr17~212 } "NODE_NAME" } } { "ps2_keyboard_interface.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2_keyboard_interface.v" 586 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.188 ns) + CELL(0.589 ns) 7.245 ns ps2_keyboard_interface:inst1\|WideOr17~217 7 COMB LAB_X29_Y21 3 " "Info: 7: + IC(0.188 ns) + CELL(0.589 ns) = 7.245 ns; Loc. = LAB_X29_Y21; Fanout = 3; COMB Node = 'ps2_keyboard_interface:inst1\|WideOr17~217'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.777 ns" { ps2_keyboard_interface:inst1|WideOr17~212 ps2_keyboard_interface:inst1|WideOr17~217 } "NODE_NAME" } } { "ps2_keyboard_interface.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2_keyboard_interface.v" 586 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.188 ns) + CELL(0.624 ns) 8.057 ns ps2_keyboard_interface:inst1\|WideNor6 8 COMB LAB_X29_Y21 2 " "Info: 8: + IC(0.188 ns) + CELL(0.624 ns) = 8.057 ns; Loc. = LAB_X29_Y21; Fanout = 2; COMB Node = 'ps2_keyboard_interface:inst1\|WideNor6'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.812 ns" { ps2_keyboard_interface:inst1|WideOr17~217 ps2_keyboard_interface:inst1|WideNor6 } "NODE_NAME" } } { "ps2_keyboard_interface.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2_keyboard_interface.v" 586 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.161 ns) + CELL(0.614 ns) 8.832 ns ps2_keyboard_interface:inst1\|WideOr19~154 9 COMB LAB_X29_Y21 2 " "Info: 9: + IC(0.161 ns) + CELL(0.614 ns) = 8.832 ns; Loc. = LAB_X29_Y21; Fanout = 2; COMB Node = 'ps2_keyboard_interface:inst1\|WideOr19~154'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.775 ns" { ps2_keyboard_interface:inst1|WideNor6 ps2_keyboard_interface:inst1|WideOr19~154 } "NODE_NAME" } } { "ps2_keyboard_interface.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2_keyboard_interface.v" 586 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.442 ns) + CELL(0.370 ns) 9.644 ns ps2_keyboard_interface:inst1\|WideOr19 10 COMB LAB_X29_Y21 1 " "Info: 10: + IC(0.442 ns) + CELL(0.370 ns) = 9.644 ns; Loc. = LAB_X29_Y21; Fanout = 1; COMB Node = 'ps2_keyboard_interface:inst1\|WideOr19'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.812 ns" { ps2_keyboard_interface:inst1|WideOr19~154 ps2_keyboard_interface:inst1|WideOr19 } "NODE_NAME" } } { "ps2_keyboard_interface.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2_keyboard_interface.v" 586 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 9.752 ns ps2_keyboard_interface:inst1\|rx_ascii\[1\] 11 REG LAB_X29_Y21 3 " "Info: 11: + IC(0.000 ns) + CELL(0.108 ns) = 9.752 ns; Loc. = LAB_X29_Y21; Fanout = 3; REG Node = 'ps2_keyboard_interface:inst1\|rx_ascii\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { ps2_keyboard_interface:inst1|WideOr19 ps2_keyboard_interface:inst1|rx_ascii[1] } "NODE_NAME" } } { "ps2_keyboard_interface.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2_keyboard_interface.v" 557 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.413 ns ( 45.25 % ) " "Info: Total cell delay = 4.413 ns ( 45.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.339 ns ( 54.75 % ) " "Info: Total interconnect delay = 5.339 ns ( 54.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.752 ns" { ps2_keyboard_interface:inst1|q[8] ps2_keyboard_interface:inst1|always10~34 ps2_keyboard_interface:inst1|Equal71~6126 ps2_keyboard_interface:inst1|Equal71~6178 ps2_keyboard_interface:inst1|WideOr17~211 ps2_keyboard_interface:inst1|WideOr17~212 ps2_keyboard_interface:inst1|WideOr17~217 ps2_keyboard_interface:inst1|WideNor6 ps2_keyboard_interface:inst1|WideOr19~154 ps2_keyboard_interface:inst1|WideOr19 ps2_keyboard_interface:inst1|rx_ascii[1] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 3 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 3%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x22_y12 x32_y23 " "Info: The peak interconnect region extends from location x22_y12 to location x32_y23" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}