📄 ps2rs232.fit.qmsg
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{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "uart_if:inst3\|uart:U1\|rcvr:u1\|clkdiv\[3\] " "Info: Automatically promoted node uart_if:inst3\|uart:U1\|rcvr:u1\|clkdiv\[3\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "uart_if:inst3\|uart:U1\|rcvr:u1\|clkdiv\[3\]~349 " "Info: Destination node uart_if:inst3\|uart:U1\|rcvr:u1\|clkdiv\[3\]~349" { } { { "rcvr.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/rcvr.v" 37 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "uart_if:inst3\|uart:U1\|rcvr:u1\|clkdiv\[3\]~349" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { uart_if:inst3|uart:U1|rcvr:u1|clkdiv[3]~349 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { uart_if:inst3|uart:U1|rcvr:u1|clkdiv[3]~349 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} } { } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0} } { { "rcvr.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/rcvr.v" 37 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "uart_if:inst3\|uart:U1\|rcvr:u1\|clkdiv\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { uart_if:inst3|uart:U1|rcvr:u1|clkdiv[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { uart_if:inst3|uart:U1|rcvr:u1|clkdiv[3] } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "uart_if:inst3\|uart:U1\|txmit:u2\|clkdiv\[3\] " "Info: Automatically promoted node uart_if:inst3\|uart:U1\|txmit:u2\|clkdiv\[3\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "uart_if:inst3\|uart:U1\|txmit:u2\|clkdiv\[3\]~205 " "Info: Destination node uart_if:inst3\|uart:U1\|txmit:u2\|clkdiv\[3\]~205" { } { { "txmit.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/txmit.v" 31 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "uart_if:inst3\|uart:U1\|txmit:u2\|clkdiv\[3\]~205" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { uart_if:inst3|uart:U1|txmit:u2|clkdiv[3]~205 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { uart_if:inst3|uart:U1|txmit:u2|clkdiv[3]~205 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} } { } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0} } { { "txmit.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/txmit.v" 31 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "uart_if:inst3\|uart:U1\|txmit:u2\|clkdiv\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { uart_if:inst3|uart:U1|txmit:u2|clkdiv[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { uart_if:inst3|uart:U1|txmit:u2|clkdiv[3] } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ps2_keyboard_interface:inst1\|rx_released " "Info: Automatically promoted node ps2_keyboard_interface:inst1\|rx_released " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "uart_if:inst3\|uart:U1\|txmit:u2\|no_bits_sent~0 " "Info: Destination node uart_if:inst3\|uart:U1\|txmit:u2\|no_bits_sent~0" { } { { "txmit.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/txmit.v" 34 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "uart_if:inst3\|uart:U1\|txmit:u2\|no_bits_sent~0" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { uart_if:inst3|uart:U1|txmit:u2|no_bits_sent~0 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { uart_if:inst3|uart:U1|txmit:u2|no_bits_sent~0 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2_keyboard_interface:inst1\|rx_released~388 " "Info: Destination node ps2_keyboard_interface:inst1\|rx_released~388" { } { { "ps2_keyboard_interface.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2_keyboard_interface.v" 188 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ps2_keyboard_interface:inst1\|rx_released~388" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ps2_keyboard_interface:inst1|rx_released~388 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ps2_keyboard_interface:inst1|rx_released~388 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "data_buf:inst5\|data_in_buf\[0\]~890 " "Info: Destination node data_buf:inst5\|data_in_buf\[0\]~890" { } { { "data_buf.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/data_buf.v" 11 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "data_buf:inst5\|data_in_buf\[0\]~890" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { data_buf:inst5|data_in_buf[0]~890 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { data_buf:inst5|data_in_buf[0]~890 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "uart_if:inst3\|read_once " "Info: Destination node uart_if:inst3\|read_once" { } { { "uart_if.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/uart_if.v" 25 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "uart_if:inst3\|read_once" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { uart_if:inst3|read_once } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { uart_if:inst3|read_once } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "data_buf:inst5\|data_in_buf\[1\]~891 " "Info: Destination node data_buf:inst5\|data_in_buf\[1\]~891" { } { { "data_buf.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/data_buf.v" 11 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "data_buf:inst5\|data_in_buf\[1\]~891" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { data_buf:inst5|data_in_buf[1]~891 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { data_buf:inst5|data_in_buf[1]~891 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "data_buf:inst5\|data_in_buf\[2\]~892 " "Info: Destination node data_buf:inst5\|data_in_buf\[2\]~892" { } { { "data_buf.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/data_buf.v" 11 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "data_buf:inst5\|data_in_buf\[2\]~892" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { data_buf:inst5|data_in_buf[2]~892 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { data_buf:inst5|data_in_buf[2]~892 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "uart_if:inst3\|uart:U1\|rcvr:u1\|data_ready~0 " "Info: Destination node uart_if:inst3\|uart:U1\|rcvr:u1\|data_ready~0" { } { { "rcvr.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/rcvr.v" 30 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "uart_if:inst3\|uart:U1\|rcvr:u1\|data_ready~0" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { uart_if:inst3|uart:U1|rcvr:u1|data_ready~0 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { uart_if:inst3|uart:U1|rcvr:u1|data_ready~0 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "uart_if:inst3\|uart:U1\|rcvr:u1\|no_bits_rcvd~0 " "Info: Destination node uart_if:inst3\|uart:U1\|rcvr:u1\|no_bits_rcvd~0" { } { { "rcvr.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/rcvr.v" 40 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "uart_if:inst3\|uart:U1\|rcvr:u1\|no_bits_rcvd~0" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { uart_if:inst3|uart:U1|rcvr:u1|no_bits_rcvd~0 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { uart_if:inst3|uart:U1|rcvr:u1|no_bits_rcvd~0 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "data_buf:inst5\|data_in_buf\[3\]~893 " "Info: Destination node data_buf:inst5\|data_in_buf\[3\]~893" { } { { "data_buf.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/data_buf.v" 11 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "data_buf:inst5\|data_in_buf\[3\]~893" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { data_buf:inst5|data_in_buf[3]~893 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { data_buf:inst5|data_in_buf[3]~893 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "data_buf:inst5\|data_in_buf\[4\]~894 " "Info: Destination node data_buf:inst5\|data_in_buf\[4\]~894" { } { { "data_buf.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/data_buf.v" 11 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "data_buf:inst5\|data_in_buf\[4\]~894" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { data_buf:inst5|data_in_buf[4]~894 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { data_buf:inst5|data_in_buf[4]~894 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Info: Non-global destination nodes limited to 10 nodes" { } { } 0 0 "Non-global destination nodes limited to %1!d! nodes" 0 0} } { } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0} } { { "ps2_keyboard_interface.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/ps2_keyboard_interface.v" 188 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ps2_keyboard_interface:inst1\|rx_released" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ps2_keyboard_interface:inst1|rx_released } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ps2_keyboard_interface:inst1|rx_released } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "uart_if:inst3\|wrn " "Info: Automatically promoted node uart_if:inst3\|wrn " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "uart_if:inst3\|uart:U1\|txmit:u2\|wrn1 " "Info: Destination node uart_if:inst3\|uart:U1\|txmit:u2\|wrn1" { } { { "txmit.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/txmit.v" 35 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "uart_if:inst3\|uart:U1\|txmit:u2\|wrn1" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { uart_if:inst3|uart:U1|txmit:u2|wrn1 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { uart_if:inst3|uart:U1|txmit:u2|wrn1 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0} } { } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0} } { { "uart_if.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/uart_if.v" 17 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "uart_if:inst3\|wrn" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { uart_if:inst3|wrn } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { uart_if:inst3|wrn } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "uart_if:inst3\|uart:U1\|rcvr:u1\|no_bits_rcvd~0 " "Info: Automatically promoted node uart_if:inst3\|uart:U1\|rcvr:u1\|no_bits_rcvd~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} } { { "rcvr.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/rcvr.v" 40 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "uart_if:inst3\|uart:U1\|rcvr:u1\|no_bits_rcvd~0" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { uart_if:inst3|uart:U1|rcvr:u1|no_bits_rcvd~0 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { uart_if:inst3|uart:U1|rcvr:u1|no_bits_rcvd~0 } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "uart_if:inst3\|uart:U1\|txmit:u2\|no_bits_sent~0 " "Info: Automatically promoted node uart_if:inst3\|uart:U1\|txmit:u2\|no_bits_sent~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} } { { "txmit.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/ps2rs232/txmit.v" 34 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "uart_if:inst3\|uart:U1\|txmit:u2\|no_bits_sent~0" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { uart_if:inst3|uart:U1|txmit:u2|no_bits_sent~0 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { uart_if:inst3|uart:U1|txmit:u2|no_bits_sent~0 } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0}
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