pskfsk.tan.qmsg

FSK和PSK调制与解调的VHDL源程序.是在QUARTUS2环境下开发的.

{ "Info" "ITDB_TSU_RESULT" "altsyncram:Mux_rtl_0\|altsyncram_36j:auto_generated\|ram_block1a0~porta_address_reg4 MODE MODE 2.884 ns memory " "Info: tsu for memory \"altsyncram:Mux_rtl_0\|altsyncram_36j:auto_generated\|ram_block1a0~porta_address_reg4\" (data pin = \"MODE\", clock pin = \"MODE\") is 2.884 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.509 ns + Longest pin memory " "Info: + Longest pin to memory delay is 10.509 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns MODE 1 CLK PIN_47 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_47; Fanout = 2; CLK Node = 'MODE'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "" { MODE } "NODE_NAME" } "" } } { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.835 ns) + CELL(0.590 ns) 7.900 ns process5~30 2 COMB LC_X16_Y4_N0 14 " "Info: 2: + IC(5.835 ns) + CELL(0.590 ns) = 7.900 ns; Loc. = LC_X16_Y4_N0; Fanout = 14; COMB Node = 'process5~30'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "6.425 ns" { MODE process5~30 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.852 ns) + CELL(0.442 ns) 9.194 ns COUNT100~225 3 COMB LC_X15_Y4_N8 1 " "Info: 3: + IC(0.852 ns) + CELL(0.442 ns) = 9.194 ns; Loc. = LC_X15_Y4_N8; Fanout = 1; COMB Node = 'COUNT100~225'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "1.294 ns" { process5~30 COUNT100~225 } "NODE_NAME" } "" } } { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.932 ns) + CELL(0.383 ns) 10.509 ns altsyncram:Mux_rtl_0\|altsyncram_36j:auto_generated\|ram_block1a0~porta_address_reg4 4 MEM M4K_X13_Y4 8 " "Info: 4: + IC(0.932 ns) + CELL(0.383 ns) = 10.509 ns; Loc. = M4K_X13_Y4; Fanout = 8; MEM Node = 'altsyncram:Mux_rtl_0\|altsyncram_36j:auto_generated\|ram_block1a0~porta_address_reg4'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "1.315 ns" { COUNT100~225 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } "" } } { "db/altsyncram_36j.tdf" "" { Text "D:/QQQ/fskpsk1/db/altsyncram_36j.tdf" 41 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.890 ns 27.50 % " "Info: Total cell delay = 2.890 ns ( 27.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.619 ns 72.50 % " "Info: Total interconnect delay = 7.619 ns ( 72.50 % )" {  } {  } 0}  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "10.509 ns" { MODE process5~30 COUNT100~225 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.509 ns" { MODE MODE~out0 process5~30 COUNT100~225 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg4 } { 0.000ns 0.000ns 5.835ns 0.852ns 0.932ns } { 0.000ns 1.475ns 0.590ns 0.442ns 0.383ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_36j.tdf" "" { Text "D:/QQQ/fskpsk1/db/altsyncram_36j.tdf" 41 2 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MODE destination 7.718 ns - Shortest memory " "Info: - Shortest clock path from clock \"MODE\" to destination memory is 7.718 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns MODE 1 CLK PIN_47 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_47; Fanout = 2; CLK Node = 'MODE'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "" { MODE } "NODE_NAME" } "" } } { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.667 ns) + CELL(0.442 ns) 3.584 ns SINCLK~68 2 COMB LC_X8_Y6_N5 15 " "Info: 2: + IC(1.667 ns) + CELL(0.442 ns) = 3.584 ns; Loc. = LC_X8_Y6_N5; Fanout = 15; COMB Node = 'SINCLK~68'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "2.109 ns" { MODE SINCLK~68 } "NODE_NAME" } "" } } { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.412 ns) + CELL(0.722 ns) 7.718 ns altsyncram:Mux_rtl_0\|altsyncram_36j:auto_generated\|ram_block1a0~porta_address_reg4 3 MEM M4K_X13_Y4 8 " "Info: 3: + IC(3.412 ns) + CELL(0.722 ns) = 7.718 ns; Loc. = M4K_X13_Y4; Fanout = 8; MEM Node = 'altsyncram:Mux_rtl_0\|altsyncram_36j:auto_generated\|ram_block1a0~porta_address_reg4'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "4.134 ns" { SINCLK~68 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } "" } } { "db/altsyncram_36j.tdf" "" { Text "D:/QQQ/fskpsk1/db/altsyncram_36j.tdf" 41 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.639 ns 34.19 % " "Info: Total cell delay = 2.639 ns ( 34.19 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.079 ns 65.81 % " "Info: Total interconnect delay = 5.079 ns ( 65.81 % )" {  } {  } 0}  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "7.718 ns" { MODE SINCLK~68 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.718 ns" { MODE MODE~out0 SINCLK~68 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg4 } { 0.000ns 0.000ns 1.667ns 3.412ns } { 0.000ns 1.475ns 0.442ns 0.722ns } } }  } 0}  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "10.509 ns" { MODE process5~30 COUNT100~225 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.509 ns" { MODE MODE~out0 process5~30 COUNT100~225 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg4 } { 0.000ns 0.000ns 5.835ns 0.852ns 0.932ns } { 0.000ns 1.475ns 0.590ns 0.442ns 0.383ns } } } { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "7.718 ns" { MODE SINCLK~68 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.718 ns" { MODE MODE~out0 SINCLK~68 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg4 } { 0.000ns 0.000ns 1.667ns 3.412ns } { 0.000ns 1.475ns 0.442ns 0.722ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK VALUE\[4\] altsyncram:Mux_rtl_0\|altsyncram_36j:auto_generated\|ram_block1a0~porta_address_reg0 29.939 ns memory " "Info: tco from clock \"CLOCK\" to destination pin \"VALUE\[4\]\" through memory \"altsyncram:Mux_rtl_0\|altsyncram_36j:auto_generated\|ram_block1a0~porta_address_reg0\" is 29.939 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK source 20.455 ns + Longest memory " "Info: + Longest clock path from clock \"CLOCK\" to source memory is 20.455 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLOCK 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'CLOCK'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "" { CLOCK } "NODE_NAME" } "" } } { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.935 ns) 2.962 ns CLK240~reg0 2 REG LC_X11_Y6_N2 4 " "Info: 2: + IC(0.558 ns) + CELL(0.935 ns) = 2.962 ns; Loc. = LC_X11_Y6_N2; Fanout = 4; REG Node = 'CLK240~reg0'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "1.493 ns" { CLOCK CLK240~reg0 } "NODE_NAME" } "" } } { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.567 ns) + CELL(0.935 ns) 4.464 ns CLK120~reg0 3 REG LC_X11_Y6_N4 10 " "Info: 3: + IC(0.567 ns) + CELL(0.935 ns) = 4.464 ns; Loc. = LC_X11_Y6_N4; Fanout = 10; REG Node = 'CLK120~reg0'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "1.502 ns" { CLK240~reg0 CLK120~reg0 } "NODE_NAME" } "" } } { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.886 ns) + CELL(0.935 ns) 9.285 ns CODERATE 4 REG LC_X8_Y6_N2 4 " "Info: 4: + IC(3.886 ns) + CELL(0.935 ns) = 9.285 ns; Loc. = LC_X8_Y6_N2; Fanout = 4; REG Node = 'CODERATE'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "4.821 ns" { CLK120~reg0 CODERATE } "NODE_NAME" } "" } } { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.461 ns) + CELL(0.935 ns) 13.681 ns M\[0\] 5 REG LC_X16_Y4_N0 6 " "Info: 5: + IC(3.461 ns) + CELL(0.935 ns) = 13.681 ns; Loc. = LC_X16_Y4_N0; Fanout = 6; REG Node = 'M\[0\]'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "4.396 ns" { CODERATE M[0] } "NODE_NAME" } "" } } { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.050 ns) + CELL(0.590 ns) 16.321 ns SINCLK~68 6 COMB LC_X8_Y6_N5 15 " "Info: 6: + IC(2.050 ns) + CELL(0.590 ns) = 16.321 ns; Loc. = LC_X8_Y6_N5; Fanout = 15; COMB Node = 'SINCLK~68'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "2.640 ns" { M[0] SINCLK~68 } "NODE_NAME" } "" } } { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.412 ns) + CELL(0.722 ns) 20.455 ns altsyncram:Mux_rtl_0\|altsyncram_36j:auto_generated\|ram_block1a0~porta_address_reg0 7 MEM M4K_X13_Y4 8 " "Info: 7: + IC(3.412 ns) + CELL(0.722 ns) = 20.455 ns; Loc. = M4K_X13_Y4; Fanout = 8; MEM Node = 'altsyncram:Mux_rtl_0\|altsyncram_36j:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "4.134 ns" { SINCLK~68 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_36j.tdf" "" { Text "D:/QQQ/fskpsk1/db/altsyncram_36j.tdf" 41 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.521 ns 31.88 % " "Info: Total cell delay = 6.521 ns ( 31.88 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.934 ns 68.12 % " "Info: Total interconnect delay = 13.934 ns ( 68.12 % )" {  } {  } 0}  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "20.455 ns" { CLOCK CLK240~reg0 CLK120~reg0 CODERATE M[0] SINCLK~68 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "20.455 ns" { CLOCK CLOCK~out0 CLK240~reg0 CLK120~reg0 CODERATE M[0] SINCLK~68 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.558ns 0.567ns 3.886ns 3.461ns 2.050ns 3.412ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.590ns 0.722ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_36j.tdf" "" { Text "D:/QQQ/fskpsk1/db/altsyncram_36j.tdf" 41 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.834 ns + Longest memory pin " "Info: + Longest memory to pin delay is 8.834 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:Mux_rtl_0\|altsyncram_36j:auto_generated\|ram_block1a0~porta_address_reg0 1 MEM M4K_X13_Y4 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y4; Fanout = 8; MEM Node = 'altsyncram:Mux_rtl_0\|altsyncram_36j:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "" { altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_36j.tdf" "" { Text "D:/QQQ/fskpsk1/db/altsyncram_36j.tdf" 41 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns altsyncram:Mux_rtl_0\|altsyncram_36j:auto_generated\|q_a\[4\] 2 MEM M4K_X13_Y4 1 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X13_Y4; Fanout = 1; MEM Node = 'altsyncram:Mux_rtl_0\|altsyncram_36j:auto_generated\|q_a\[4\]'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "4.308 ns" { altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg0 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|q_a[4] } "NODE_NAME" } "" } } { "db/altsyncram_36j.tdf" "" { Text "D:/QQQ/fskpsk1/db/altsyncram_36j.tdf" 38 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.418 ns) + CELL(2.108 ns) 8.834 ns VALUE\[4\] 3 PIN PIN_124 0 " "Info: 3: + IC(2.418 ns) + CELL(2.108 ns) = 8.834 ns; Loc. = PIN_124; Fanout = 0; PIN Node = 'VALUE\[4\]'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "4.526 ns" { altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|q_a[4] VALUE[4] } "NODE_NAME" } "" } } { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.416 ns 72.63 % " "Info: Total cell delay = 6.416 ns ( 72.63 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.418 ns 27.37 % " "Info: Total interconnect delay = 2.418 ns ( 27.37 % )" {  } {  } 0}  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "8.834 ns" { altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg0 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|q_a[4] VALUE[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.834 ns" { altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg0 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|q_a[4] VALUE[4] } { 0.000ns 0.000ns 2.418ns } { 0.000ns 4.308ns 2.108ns } } }  } 0}  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt"