pskfsk.tan.qmsg

FSK和PSK调制与解调的VHDL源程序.是在QUARTUS2环境下开发的.

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLOCK " "Info: Assuming node \"CLOCK\" is an undefined clock" {  } { { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 7 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CLOCK" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "MODE " "Info: Assuming node \"MODE\" is an undefined clock" {  } { { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 8 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "MODE" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "5 " "Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "CODERATE " "Info: Detected ripple clock \"CODERATE\" as buffer" {  } { { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 19 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CODERATE" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "M\[0\] " "Info: Detected ripple clock \"M\[0\]\" as buffer" {  } { { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 21 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "M\[0\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "SINCLK~68 " "Info: Detected gated clock \"SINCLK~68\" as buffer" {  } { { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 19 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SINCLK~68" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "CLK120~reg0 " "Info: Detected ripple clock \"CLK120~reg0\" as buffer" {  } { { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 41 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CLK120~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "CLK240~reg0 " "Info: Detected ripple clock \"CLK240~reg0\" as buffer" {  } { { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 27 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CLK240~reg0" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLOCK register COUNT100\[0\] memory altsyncram:Mux_rtl_0\|altsyncram_36j:auto_generated\|ram_block1a0~porta_address_reg2 60.09 MHz 16.643 ns Internal " "Info: Clock \"CLOCK\" has Internal fmax of 60.09 MHz between source register \"COUNT100\[0\]\" and destination memory \"altsyncram:Mux_rtl_0\|altsyncram_36j:auto_generated\|ram_block1a0~porta_address_reg2\" (period= 16.643 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.449 ns + Longest register memory " "Info: + Longest register to memory delay is 4.449 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns COUNT100\[0\] 1 REG LC_X15_Y4_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y4_N2; Fanout = 4; REG Node = 'COUNT100\[0\]'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "" { COUNT100[0] } "NODE_NAME" } "" } } { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.737 ns) + CELL(0.432 ns) 1.169 ns add~309COUT1_382 2 COMB LC_X16_Y4_N1 2 " "Info: 2: + IC(0.737 ns) + CELL(0.432 ns) = 1.169 ns; Loc. = LC_X16_Y4_N1; Fanout = 2; COMB Node = 'add~309COUT1_382'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "1.169 ns" { COUNT100[0] add~309COUT1_382 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.249 ns add~314COUT1_384 3 COMB LC_X16_Y4_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.249 ns; Loc. = LC_X16_Y4_N2; Fanout = 2; COMB Node = 'add~314COUT1_384'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "0.080 ns" { add~309COUT1_382 add~314COUT1_384 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 1.857 ns add~317 4 COMB LC_X16_Y4_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.608 ns) = 1.857 ns; Loc. = LC_X16_Y4_N3; Fanout = 2; COMB Node = 'add~317'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "0.608 ns" { add~314COUT1_384 add~317 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.706 ns) + CELL(0.590 ns) 3.153 ns COUNT100~223 5 COMB LC_X15_Y4_N5 1 " "Info: 5: + IC(0.706 ns) + CELL(0.590 ns) = 3.153 ns; Loc. = LC_X15_Y4_N5; Fanout = 1; COMB Node = 'COUNT100~223'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "1.296 ns" { add~317 COUNT100~223 } "NODE_NAME" } "" } } { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.913 ns) + CELL(0.383 ns) 4.449 ns altsyncram:Mux_rtl_0\|altsyncram_36j:auto_generated\|ram_block1a0~porta_address_reg2 6 MEM M4K_X13_Y4 8 " "Info: 6: + IC(0.913 ns) + CELL(0.383 ns) = 4.449 ns; Loc. = M4K_X13_Y4; Fanout = 8; MEM Node = 'altsyncram:Mux_rtl_0\|altsyncram_36j:auto_generated\|ram_block1a0~porta_address_reg2'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "1.296 ns" { COUNT100~223 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg2 } "NODE_NAME" } "" } } { "db/altsyncram_36j.tdf" "" { Text "D:/QQQ/fskpsk1/db/altsyncram_36j.tdf" 41 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.093 ns 47.04 % " "Info: Total cell delay = 2.093 ns ( 47.04 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.356 ns 52.96 % " "Info: Total interconnect delay = 2.356 ns ( 52.96 % )" {  } {  } 0}  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "4.449 ns" { COUNT100[0] add~309COUT1_382 add~314COUT1_384 add~317 COUNT100~223 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.449 ns" { COUNT100[0] add~309COUT1_382 add~314COUT1_384 add~317 COUNT100~223 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg2 } { 0.000ns 0.737ns 0.000ns 0.000ns 0.706ns 0.913ns } { 0.000ns 0.432ns 0.080ns 0.608ns 0.590ns 0.383ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-11.877 ns - Smallest " "Info: - Smallest clock skew is -11.877 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK destination 8.567 ns + Shortest memory " "Info: + Shortest clock path from clock \"CLOCK\" to destination memory is 8.567 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLOCK 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'CLOCK'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "" { CLOCK } "NODE_NAME" } "" } } { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.935 ns) 2.962 ns CLK240~reg0 2 REG LC_X11_Y6_N2 4 " "Info: 2: + IC(0.558 ns) + CELL(0.935 ns) = 2.962 ns; Loc. = LC_X11_Y6_N2; Fanout = 4; REG Node = 'CLK240~reg0'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "1.493 ns" { CLOCK CLK240~reg0 } "NODE_NAME" } "" } } { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.179 ns) + CELL(0.292 ns) 4.433 ns SINCLK~68 3 COMB LC_X8_Y6_N5 15 " "Info: 3: + IC(1.179 ns) + CELL(0.292 ns) = 4.433 ns; Loc. = LC_X8_Y6_N5; Fanout = 15; COMB Node = 'SINCLK~68'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "1.471 ns" { CLK240~reg0 SINCLK~68 } "NODE_NAME" } "" } } { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.412 ns) + CELL(0.722 ns) 8.567 ns altsyncram:Mux_rtl_0\|altsyncram_36j:auto_generated\|ram_block1a0~porta_address_reg2 4 MEM M4K_X13_Y4 8 " "Info: 4: + IC(3.412 ns) + CELL(0.722 ns) = 8.567 ns; Loc. = M4K_X13_Y4; Fanout = 8; MEM Node = 'altsyncram:Mux_rtl_0\|altsyncram_36j:auto_generated\|ram_block1a0~porta_address_reg2'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "4.134 ns" { SINCLK~68 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg2 } "NODE_NAME" } "" } } { "db/altsyncram_36j.tdf" "" { Text "D:/QQQ/fskpsk1/db/altsyncram_36j.tdf" 41 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.418 ns 39.90 % " "Info: Total cell delay = 3.418 ns ( 39.90 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.149 ns 60.10 % " "Info: Total interconnect delay = 5.149 ns ( 60.10 % )" {  } {  } 0}  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "8.567 ns" { CLOCK CLK240~reg0 SINCLK~68 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.567 ns" { CLOCK CLOCK~out0 CLK240~reg0 SINCLK~68 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg2 } { 0.000ns 0.000ns 0.558ns 1.179ns 3.412ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.722ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK source 20.444 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK\" to source register is 20.444 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLOCK 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'CLOCK'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "" { CLOCK } "NODE_NAME" } "" } } { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.935 ns) 2.962 ns CLK240~reg0 2 REG LC_X11_Y6_N2 4 " "Info: 2: + IC(0.558 ns) + CELL(0.935 ns) = 2.962 ns; Loc. = LC_X11_Y6_N2; Fanout = 4; REG Node = 'CLK240~reg0'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "1.493 ns" { CLOCK CLK240~reg0 } "NODE_NAME" } "" } } { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.567 ns) + CELL(0.935 ns) 4.464 ns CLK120~reg0 3 REG LC_X11_Y6_N4 10 " "Info: 3: + IC(0.567 ns) + CELL(0.935 ns) = 4.464 ns; Loc. = LC_X11_Y6_N4; Fanout = 10; REG Node = 'CLK120~reg0'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "1.502 ns" { CLK240~reg0 CLK120~reg0 } "NODE_NAME" } "" } } { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.886 ns) + CELL(0.935 ns) 9.285 ns CODERATE 4 REG LC_X8_Y6_N2 4 " "Info: 4: + IC(3.886 ns) + CELL(0.935 ns) = 9.285 ns; Loc. = LC_X8_Y6_N2; Fanout = 4; REG Node = 'CODERATE'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "4.821 ns" { CLK120~reg0 CODERATE } "NODE_NAME" } "" } } { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.461 ns) + CELL(0.935 ns) 13.681 ns M\[0\] 5 REG LC_X16_Y4_N0 6 " "Info: 5: + IC(3.461 ns) + CELL(0.935 ns) = 13.681 ns; Loc. = LC_X16_Y4_N0; Fanout = 6; REG Node = 'M\[0\]'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "4.396 ns" { CODERATE M[0] } "NODE_NAME" } "" } } { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.050 ns) + CELL(0.590 ns) 16.321 ns SINCLK~68 6 COMB LC_X8_Y6_N5 15 " "Info: 6: + IC(2.050 ns) + CELL(0.590 ns) = 16.321 ns; Loc. = LC_X8_Y6_N5; Fanout = 15; COMB Node = 'SINCLK~68'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "2.640 ns" { M[0] SINCLK~68 } "NODE_NAME" } "" } } { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.412 ns) + CELL(0.711 ns) 20.444 ns COUNT100\[0\] 7 REG LC_X15_Y4_N2 4 " "Info: 7: + IC(3.412 ns) + CELL(0.711 ns) = 20.444 ns; Loc. = LC_X15_Y4_N2; Fanout = 4; REG Node = 'COUNT100\[0\]'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "4.123 ns" { SINCLK~68 COUNT100[0] } "NODE_NAME" } "" } } { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.510 ns 31.84 % " "Info: Total cell delay = 6.510 ns ( 31.84 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.934 ns 68.16 % " "Info: Total interconnect delay = 13.934 ns ( 68.16 % )" {  } {  } 0}  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "20.444 ns" { CLOCK CLK240~reg0 CLK120~reg0 CODERATE M[0] SINCLK~68 COUNT100[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "20.444 ns" { CLOCK CLOCK~out0 CLK240~reg0 CLK120~reg0 CODERATE M[0] SINCLK~68 COUNT100[0] } { 0.000ns 0.000ns 0.558ns 0.567ns 3.886ns 3.461ns 2.050ns 3.412ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.590ns 0.711ns } } }  } 0}  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "8.567 ns" { CLOCK CLK240~reg0 SINCLK~68 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.567 ns" { CLOCK CLOCK~out0 CLK240~reg0 SINCLK~68 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg2 } { 0.000ns 0.000ns 0.558ns 1.179ns 3.412ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.722ns } } } { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "20.444 ns" { CLOCK CLK240~reg0 CLK120~reg0 CODERATE M[0] SINCLK~68 COUNT100[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "20.444 ns" { CLOCK CLOCK~out0 CLK240~reg0 CLK120~reg0 CODERATE M[0] SINCLK~68 COUNT100[0] } { 0.000ns 0.000ns 0.558ns 0.567ns 3.886ns 3.461ns 2.050ns 3.412ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.590ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_36j.tdf" "" { Text "D:/QQQ/fskpsk1/db/altsyncram_36j.tdf" 41 2 0 } }  } 0}  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "4.449 ns" { COUNT100[0] add~309COUT1_382 add~314COUT1_384 add~317 COUNT100~223 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.449 ns" { COUNT100[0] add~309COUT1_382 add~314COUT1_384 add~317 COUNT100~223 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg2 } { 0.000ns 0.737ns 0.000ns 0.000ns 0.706ns 0.913ns } { 0.000ns 0.432ns 0.080ns 0.608ns 0.590ns 0.383ns } } } { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "8.567 ns" { CLOCK CLK240~reg0 SINCLK~68 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.567 ns" { CLOCK CLOCK~out0 CLK240~reg0 SINCLK~68 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg2 } { 0.000ns 0.000ns 0.558ns 1.179ns 3.412ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.722ns } } } { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "20.444 ns" { CLOCK CLK240~reg0 CLK120~reg0 CODERATE M[0] SINCLK~68 COUNT100[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "20.444 ns" { CLOCK CLOCK~out0 CLK240~reg0 CLK120~reg0 CODERATE M[0] SINCLK~68 COUNT100[0] } { 0.000ns 0.000ns 0.558ns 0.567ns 3.886ns 3.461ns 2.050ns 3.412ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.590ns 0.711ns } } }  } 0}