pskfsk.map.eqn

FSK和PSK调制与解调的VHDL源程序.是在QUARTUS2环境下开发的.

-- Copyright (C) 1991-2005 Altera Corporation
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-- and other software and tools, and its AMPP partner logic 
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-- (including device programming or simulation files), and any 
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-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L03Q is CLK240~reg0
--operation mode is normal

A1L03Q_lut_out = A1L03Q $ (COUNT[2] & COUNT[0] & !A1L92 # !COUNT[2] & !COUNT[0] & A1L92);
A1L03Q = DFFEAS(A1L03Q_lut_out, CLOCK, VCC, , , , , , );


--A1L72Q is CLK120~reg0
--operation mode is normal

A1L72Q_lut_out = !A1L72Q;
A1L72Q = DFFEAS(A1L72Q_lut_out, A1L03Q, VCC, , , , , , );


--C1_q_a[0] is altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
C1_q_a[0]_PORT_A_address = BUS(A1L05, A1L15, A1L25, A1L35, A1L45, A1L55, A1L65);
C1_q_a[0]_PORT_A_address_reg = DFFE(C1_q_a[0]_PORT_A_address, C1_q_a[0]_clock_0, , , );
C1_q_a[0]_clock_0 = A1L27;
C1_q_a[0]_PORT_A_data_out = MEMORY(, , C1_q_a[0]_PORT_A_address_reg, , , , , , C1_q_a[0]_clock_0, , , , , );
C1_q_a[0] = C1_q_a[0]_PORT_A_data_out[0];


--C1_q_a[1] is altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
C1_q_a[1]_PORT_A_address = BUS(A1L05, A1L15, A1L25, A1L35, A1L45, A1L55, A1L65);
C1_q_a[1]_PORT_A_address_reg = DFFE(C1_q_a[1]_PORT_A_address, C1_q_a[1]_clock_0, , , );
C1_q_a[1]_clock_0 = A1L27;
C1_q_a[1]_PORT_A_data_out = MEMORY(, , C1_q_a[1]_PORT_A_address_reg, , , , , , C1_q_a[1]_clock_0, , , , , );
C1_q_a[1] = C1_q_a[1]_PORT_A_data_out[0];


--C1_q_a[2] is altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
C1_q_a[2]_PORT_A_address = BUS(A1L05, A1L15, A1L25, A1L35, A1L45, A1L55, A1L65);
C1_q_a[2]_PORT_A_address_reg = DFFE(C1_q_a[2]_PORT_A_address, C1_q_a[2]_clock_0, , , );
C1_q_a[2]_clock_0 = A1L27;
C1_q_a[2]_PORT_A_data_out = MEMORY(, , C1_q_a[2]_PORT_A_address_reg, , , , , , C1_q_a[2]_clock_0, , , , , );
C1_q_a[2] = C1_q_a[2]_PORT_A_data_out[0];


--C1_q_a[3] is altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
C1_q_a[3]_PORT_A_address = BUS(A1L05, A1L15, A1L25, A1L35, A1L45, A1L55, A1L65);
C1_q_a[3]_PORT_A_address_reg = DFFE(C1_q_a[3]_PORT_A_address, C1_q_a[3]_clock_0, , , );
C1_q_a[3]_clock_0 = A1L27;
C1_q_a[3]_PORT_A_data_out = MEMORY(, , C1_q_a[3]_PORT_A_address_reg, , , , , , C1_q_a[3]_clock_0, , , , , );
C1_q_a[3] = C1_q_a[3]_PORT_A_data_out[0];


--C1_q_a[4] is altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
C1_q_a[4]_PORT_A_address = BUS(A1L05, A1L15, A1L25, A1L35, A1L45, A1L55, A1L65);
C1_q_a[4]_PORT_A_address_reg = DFFE(C1_q_a[4]_PORT_A_address, C1_q_a[4]_clock_0, , , );
C1_q_a[4]_clock_0 = A1L27;
C1_q_a[4]_PORT_A_data_out = MEMORY(, , C1_q_a[4]_PORT_A_address_reg, , , , , , C1_q_a[4]_clock_0, , , , , );
C1_q_a[4] = C1_q_a[4]_PORT_A_data_out[0];


--C1_q_a[5] is altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
C1_q_a[5]_PORT_A_address = BUS(A1L05, A1L15, A1L25, A1L35, A1L45, A1L55, A1L65);
C1_q_a[5]_PORT_A_address_reg = DFFE(C1_q_a[5]_PORT_A_address, C1_q_a[5]_clock_0, , , );
C1_q_a[5]_clock_0 = A1L27;
C1_q_a[5]_PORT_A_data_out = MEMORY(, , C1_q_a[5]_PORT_A_address_reg, , , , , , C1_q_a[5]_clock_0, , , , , );
C1_q_a[5] = C1_q_a[5]_PORT_A_data_out[0];


--C1_q_a[6] is altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
C1_q_a[6]_PORT_A_address = BUS(A1L05, A1L15, A1L25, A1L35, A1L45, A1L55, A1L65);
C1_q_a[6]_PORT_A_address_reg = DFFE(C1_q_a[6]_PORT_A_address, C1_q_a[6]_clock_0, , , );
C1_q_a[6]_clock_0 = A1L27;
C1_q_a[6]_PORT_A_data_out = MEMORY(, , C1_q_a[6]_PORT_A_address_reg, , , , , , C1_q_a[6]_clock_0, , , , , );
C1_q_a[6] = C1_q_a[6]_PORT_A_data_out[0];


--C1_q_a[7] is altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
C1_q_a[7]_PORT_A_address = BUS(A1L05, A1L15, A1L25, A1L35, A1L45, A1L55, A1L65);
C1_q_a[7]_PORT_A_address_reg = DFFE(C1_q_a[7]_PORT_A_address, C1_q_a[7]_clock_0, , , );
C1_q_a[7]_clock_0 = A1L27;
C1_q_a[7]_PORT_A_data_out = MEMORY(, , C1_q_a[7]_PORT_A_address_reg, , , , , , C1_q_a[7]_clock_0, , , , , );
C1_q_a[7] = C1_q_a[7]_PORT_A_data_out[0];


--M[0] is M[0]
--operation mode is normal

M[0]_lut_out = M[1];
M[0] = DFFEAS(M[0]_lut_out, CODERATE, VCC, , , , , , );


--COUNT[2] is COUNT[2]
--operation mode is normal

COUNT[2]_lut_out = !COUNT[2];
COUNT[2] = DFFEAS(COUNT[2]_lut_out, CLOCK, VCC, , A1L41, , , , );


--COUNT[0] is COUNT[0]
--operation mode is normal

COUNT[0]_lut_out = !COUNT[0];
COUNT[0] = DFFEAS(COUNT[0]_lut_out, CLOCK, VCC, , , , , , );


--COUNT[1] is COUNT[1]
--operation mode is normal

COUNT[1]_lut_out = COUNT[0] & (!COUNT[1]) # !COUNT[0] & COUNT[1] & (COUNT[2] # !COUNT[3]);
COUNT[1] = DFFEAS(COUNT[1]_lut_out, CLOCK, VCC, , , , , , );


--COUNT[3] is COUNT[3]
--operation mode is normal

COUNT[3]_lut_out = COUNT[3] & (COUNT[2] $ COUNT[0] # !COUNT[1]) # !COUNT[3] & COUNT[2] & COUNT[0] & COUNT[1];
COUNT[3] = DFFEAS(COUNT[3]_lut_out, CLOCK, VCC, , , , , , );


--A1L92 is CLK240~246
--operation mode is normal

A1L92 = COUNT[0] & (COUNT[1] # COUNT[3]) # !COUNT[0] & COUNT[1] & COUNT[3];


--A1L27 is SINCLK~68
--operation mode is normal

A1L27 = M[0] & A1L03Q # !M[0] & (MODE & A1L03Q # !MODE & (A1L72Q));


--A1L1 is add~307
--operation mode is arithmetic

A1L1 = !COUNT100[0];

--A1L2 is add~309
--operation mode is arithmetic

A1L2 = CARRY(COUNT100[0]);


--TEMP is TEMP
--operation mode is normal

TEMP_lut_out = M[0];
TEMP = DFFEAS(TEMP_lut_out, A1L27, VCC, , , , , , );


--A1L76 is process5~30
--operation mode is normal

A1L76 = M[0] # !TEMP # !MODE;


--COUNT100[4] is COUNT100[4]
--operation mode is normal

COUNT100[4]_lut_out = A1L45;
COUNT100[4] = DFFEAS(COUNT100[4]_lut_out, A1L27, VCC, , , , , , );


--COUNT100[3] is COUNT100[3]
--operation mode is normal

COUNT100[3]_lut_out = A1L35;
COUNT100[3] = DFFEAS(COUNT100[3]_lut_out, A1L27, VCC, , , , , , );


--COUNT100[6] is COUNT100[6]
--operation mode is normal

COUNT100[6]_lut_out = A1L65;
COUNT100[6] = DFFEAS(COUNT100[6]_lut_out, A1L27, VCC, , , , , , );


--COUNT100[5] is COUNT100[5]
--operation mode is normal

COUNT100[5]_lut_out = A1L55;
COUNT100[5] = DFFEAS(COUNT100[5]_lut_out, A1L27, VCC, , , , , , );


--A1L96 is reduce_nor~99
--operation mode is normal

A1L96 = COUNT100[4] # COUNT100[3] # !COUNT100[5] # !COUNT100[6];


--COUNT100[2] is COUNT100[2]
--operation mode is normal

COUNT100[2]_lut_out = A1L25;
COUNT100[2] = DFFEAS(COUNT100[2]_lut_out, A1L27, VCC, , , , , , );


--COUNT100[1] is COUNT100[1]
--operation mode is normal

COUNT100[1]_lut_out = A1L15;
COUNT100[1] = DFFEAS(COUNT100[1]_lut_out, A1L27, VCC, , , , , , );


--COUNT100[0] is COUNT100[0]
--operation mode is normal

COUNT100[0]_lut_out = A1L05;
COUNT100[0] = DFFEAS(COUNT100[0]_lut_out, A1L27, VCC, , , , , , );


--A1L07 is reduce_nor~100
--operation mode is normal

A1L07 = COUNT100[2] # !COUNT100[0] # !COUNT100[1];


--A1L94 is COUNT100~220
--operation mode is normal

A1L94 = TEMP & (A1L96 # A1L07) # !TEMP & !M[0] & (A1L96 # A1L07);


--A1L05 is COUNT100~221
--operation mode is normal

A1L05 = A1L1 & A1L76 & A1L94;


--A1L3 is add~312
--operation mode is arithmetic

A1L3_carry_eqn = A1L2;
A1L3 = COUNT100[1] $ (A1L3_carry_eqn);

--A1L4 is add~314
--operation mode is arithmetic

A1L4 = CARRY(!A1L2 # !COUNT100[1]);


--A1L15 is COUNT100~222
--operation mode is normal

A1L15 = A1L94 & (A1L3 # !A1L76);


--A1L5 is add~317
--operation mode is arithmetic

A1L5_carry_eqn = A1L4;
A1L5 = COUNT100[2] $ (!A1L5_carry_eqn);

--A1L6 is add~319
--operation mode is arithmetic

A1L6 = CARRY(COUNT100[2] & (!A1L4));


--A1L25 is COUNT100~223
--operation mode is normal

A1L25 = A1L5 & A1L76 & A1L94;


--A1L7 is add~322
--operation mode is arithmetic

A1L7_carry_eqn = A1L6;
A1L7 = COUNT100[3] $ (A1L7_carry_eqn);

--A1L8 is add~324
--operation mode is arithmetic

A1L8 = CARRY(!A1L6 # !COUNT100[3]);


--A1L35 is COUNT100~224
--operation mode is normal

A1L35 = A1L7 & A1L76 & A1L94;


--A1L9 is add~327
--operation mode is arithmetic

A1L9_carry_eqn = A1L8;
A1L9 = COUNT100[4] $ (!A1L9_carry_eqn);

--A1L01 is add~329
--operation mode is arithmetic

A1L01 = CARRY(COUNT100[4] & (!A1L8));


--A1L45 is COUNT100~225
--operation mode is normal

A1L45 = A1L94 & (A1L9 # !A1L76);


--A1L11 is add~332
--operation mode is arithmetic

A1L11_carry_eqn = A1L01;
A1L11 = COUNT100[5] $ (A1L11_carry_eqn);

--A1L21 is add~334
--operation mode is arithmetic

A1L21 = CARRY(!A1L01 # !COUNT100[5]);


--A1L55 is COUNT100~226
--operation mode is normal

A1L55 = A1L94 & (A1L11 # !A1L76);


--A1L31 is add~337
--operation mode is normal

A1L31_carry_eqn = A1L21;
A1L31 = COUNT100[6] $ (!A1L31_carry_eqn);


--A1L65 is COUNT100~227
--operation mode is normal

A1L65 = A1L31 & A1L76 & A1L94;


--M[1] is M[1]
--operation mode is normal

M[1]_lut_out = M[2];
M[1] = DFFEAS(M[1]_lut_out, CODERATE, VCC, , , , , , );


--CODERATE is CODERATE
--operation mode is normal

CODERATE_lut_out = !CODERATE;
CODERATE = DFFEAS(CODERATE_lut_out, A1L72Q, VCC, , A1L86, , , , );


--A1L41 is add~342
--operation mode is normal

A1L41 = COUNT[1] & COUNT[0];


--M[2] is M[2]
--operation mode is normal

M[2]_lut_out = M[0] & (!M[1]) # !M[0] & (M[1] # !M[2]);
M[2] = DFFEAS(M[2]_lut_out, CODERATE, VCC, , , , , , );


--COUNT50[3] is COUNT50[3]
--operation mode is normal

COUNT50[3]_lut_out = A1L51;
COUNT50[3] = DFFEAS(COUNT50[3]_lut_out, A1L72Q, VCC, , , , , , );


--COUNT50[2] is COUNT50[2]
--operation mode is normal

COUNT50[2]_lut_out = A1L71;
COUNT50[2] = DFFEAS(COUNT50[2]_lut_out, A1L72Q, VCC, , , , , , );


--COUNT50[5] is COUNT50[5]
--operation mode is normal

COUNT50[5]_lut_out = A1L91 & (A1L17 # COUNT50[1] # !COUNT50[0]);
COUNT50[5] = DFFEAS(COUNT50[5]_lut_out, A1L72Q, VCC, , , , , , );


--COUNT50[4] is COUNT50[4]
--operation mode is normal

COUNT50[4]_lut_out = A1L02 & (A1L17 # COUNT50[1] # !COUNT50[0]);
COUNT50[4] = DFFEAS(COUNT50[4]_lut_out, A1L72Q, VCC, , , , , , );


--A1L17 is reduce_nor~101
--operation mode is normal

A1L17 = COUNT50[3] # COUNT50[2] # !COUNT50[4] # !COUNT50[5];


--COUNT50[1] is COUNT50[1]
--operation mode is normal

COUNT50[1]_lut_out = A1L22 & (A1L17 # COUNT50[1] # !COUNT50[0]);
COUNT50[1] = DFFEAS(COUNT50[1]_lut_out, A1L72Q, VCC, , , , , , );


--COUNT50[0] is COUNT50[0]
--operation mode is normal

COUNT50[0]_lut_out = A1L42;
COUNT50[0] = DFFEAS(COUNT50[0]_lut_out, A1L72Q, VCC, , , , , , );


--A1L86 is reduce_nor~2
--operation mode is normal

A1L86 = !A1L17 & !COUNT50[1] & (COUNT50[0]);


--A1L51 is add~343
--operation mode is arithmetic

A1L51_carry_eqn = A1L81;
A1L51 = COUNT50[3] $ (A1L51_carry_eqn);

--A1L61 is add~345
--operation mode is arithmetic

A1L61 = CARRY(!A1L81 # !COUNT50[3]);


--A1L71 is add~348
--operation mode is arithmetic

A1L71_carry_eqn = A1L32;
A1L71 = COUNT50[2] $ (!A1L71_carry_eqn);

--A1L81 is add~350
--operation mode is arithmetic

A1L81 = CARRY(COUNT50[2] & (!A1L32));


--A1L91 is add~353
--operation mode is normal

A1L91_carry_eqn = A1L12;
A1L91 = COUNT50[5] $ (A1L91_carry_eqn);


--A1L02 is add~358
--operation mode is arithmetic

A1L02_carry_eqn = A1L61;
A1L02 = COUNT50[4] $ (!A1L02_carry_eqn);

--A1L12 is add~360
--operation mode is arithmetic

A1L12 = CARRY(COUNT50[4] & (!A1L61));


--A1L22 is add~363
--operation mode is arithmetic

A1L22_carry_eqn = A1L52;
A1L22 = COUNT50[1] $ (A1L22_carry_eqn);

--A1L32 is add~365
--operation mode is arithmetic

A1L32 = CARRY(!A1L52 # !COUNT50[1]);


--A1L42 is add~368
--operation mode is arithmetic

A1L42 = !COUNT50[0];

--A1L52 is add~370
--operation mode is arithmetic

A1L52 = CARRY(COUNT50[0]);


--CLOCK is CLOCK
--operation mode is input

CLOCK = INPUT();


--MODE is MODE
--operation mode is input

MODE = INPUT();


--CLK240 is CLK240
--operation mode is output

CLK240 = OUTPUT(A1L03Q);


--CLK120 is CLK120
--operation mode is output

CLK120 = OUTPUT(A1L72Q);


--VALUE[0] is VALUE[0]
--operation mode is output

VALUE[0] = OUTPUT(C1_q_a[0]);


--VALUE[1] is VALUE[1]
--operation mode is output

VALUE[1] = OUTPUT(C1_q_a[1]);


--VALUE[2] is VALUE[2]
--operation mode is output

VALUE[2] = OUTPUT(C1_q_a[2]);


--VALUE[3] is VALUE[3]
--operation mode is output

VALUE[3] = OUTPUT(C1_q_a[3]);


--VALUE[4] is VALUE[4]
--operation mode is output

VALUE[4] = OUTPUT(C1_q_a[4]);


--VALUE[5] is VALUE[5]
--operation mode is output

VALUE[5] = OUTPUT(C1_q_a[5]);


--VALUE[6] is VALUE[6]
--operation mode is output

VALUE[6] = OUTPUT(C1_q_a[6]);


--VALUE[7] is VALUE[7]
--operation mode is output

VALUE[7] = OUTPUT(C1_q_a[7]);


--M_CODE is M_CODE
--operation mode is output

M_CODE = OUTPUT(M[0]);