📄 pskfsk.fit.rpt
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; 10 ; 1 ;
; 11 ; 1 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 0 ;
; 17 ; 0 ;
; 18 ; 1 ;
+---------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out (Average = 4.88) ; Number of LABs (Total = 8) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 2 ;
; 2 ; 1 ;
; 3 ; 2 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 1 ;
+-------------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs (Average = 5.00) ; Number of LABs (Total = 8) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 2 ;
; 3 ; 1 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
; 11 ; 1 ;
+---------------------------------------------+-----------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Wed Nov 02 11:54:09 2005
Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off PSKFSK -c PSKFSK
Info: Selected device EP1C3T144C8 for design "PSKFSK"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EP1C6T144C8 is compatible
Info: No exact pin location assignment(s) for 12 pins of 13 total pins
Info: Pin CLK240 not assigned to an exact location on the device
Info: Pin VALUE[0] not assigned to an exact location on the device
Info: Pin VALUE[1] not assigned to an exact location on the device
Info: Pin VALUE[2] not assigned to an exact location on the device
Info: Pin VALUE[3] not assigned to an exact location on the device
Info: Pin VALUE[4] not assigned to an exact location on the device
Info: Pin VALUE[5] not assigned to an exact location on the device
Info: Pin VALUE[6] not assigned to an exact location on the device
Info: Pin VALUE[7] not assigned to an exact location on the device
Info: Pin M_CODE not assigned to an exact location on the device
Info: Pin CLOCK not assigned to an exact location on the device
Info: Pin MODE not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Not setting a global tsu requirement
Info: Not setting a global tco requirement
Info: Not setting a global tpd requirement
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources.
Info: Automatically promoted signal "CLOCK" to use Global clock in PIN 17
Info: Automatically promoted signal "SINCLK~68" to use Global clock
Info: Automatically promoted some destinations of signal "CLK120~reg0" to use Global clock
Info: Destination "CLK120" may be non-global or may not use global clock
Info: Destination "CLK120~reg0" may be non-global or may not use global clock
Info: Destination "SINCLK~68" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "CODERATE" to use Global clock
Info: Destination "CODERATE" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info: Number of I/O pins in group: 11 (unused VREF, 3.30 VCCIO, 1 input, 10 output, 0 bidirectional)
Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 4 total pin(s) used -- 18 pins available
Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 28 pins available
Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 26 pins available
Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 28 pins available
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to memory delay of 3.834 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y4; Fanout = 4; REG Node = 'COUNT100[0]'
Info: 2: + IC(0.704 ns) + CELL(0.575 ns) = 1.279 ns; Loc. = LAB_X16_Y4; Fanout = 2; COMB Node = 'add~309COUT1_382'
Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.359 ns; Loc. = LAB_X16_Y4; Fanout = 2; COMB Node = 'add~314COUT1_384'
Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.439 ns; Loc. = LAB_X16_Y4; Fanout = 2; COMB Node = 'add~319COUT1_385'
Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 1.697 ns; Loc. = LAB_X16_Y4; Fanout = 3; COMB Node = 'add~324'
Info: 6: + IC(0.000 ns) + CELL(0.679 ns) = 2.376 ns; Loc. = LAB_X16_Y4; Fanout = 2; COMB Node = 'add~327'
Info: 7: + IC(0.449 ns) + CELL(0.442 ns) = 3.267 ns; Loc. = LAB_X15_Y4; Fanout = 8; COMB Node = 'COUNT100~225'
Info: 8: + IC(0.184 ns) + CELL(0.383 ns) = 3.834 ns; Loc. = M4K_X13_Y4; Fanout = 1; MEM Node = 'altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg4'
Info: Total cell delay = 2.497 ns ( 65.13 % )
Info: Total interconnect delay = 1.337 ns ( 34.87 % )
Info: Fitter placement operations ending: elapsed time is 00:00:01
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%.
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Wed Nov 02 11:54:14 2005
Info: Elapsed time: 00:00:06
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