prev_cmp_fadder4.qmsg

VHDL实现四位全加器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 20 20:47:41 2008 " "Info: Processing started: Sun Apr 20 20:47:41 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off fadder4 -c fadder4 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fadder4 -c fadder4" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fadder1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fadder1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fadder1-fd " "Info: Found design unit 1: fadder1-fd" {  } { { "fadder1.vhd" "" { Text "F:/eda/fadder4/fadder1.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 fadder1 " "Info: Found entity 1: fadder1" {  } { { "fadder1.vhd" "" { Text "F:/eda/fadder4/fadder1.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fadder4.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fadder4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fadder4-behave " "Info: Found design unit 1: fadder4-behave" {  } { { "fadder4.vhd" "" { Text "F:/eda/fadder4/fadder4.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 fadder4 " "Info: Found entity 1: fadder4" {  } { { "fadder4.vhd" "" { Text "F:/eda/fadder4/fadder4.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "fadder4 " "Info: Elaborating entity \"fadder4\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fadder1 fadder1:u1 " "Info: Elaborating entity \"fadder1\" for hierarchy \"fadder1:u1\"" {  } { { "fadder4.vhd" "u1" { Text "F:/eda/fadder4/fadder4.vhd" 16 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Error" "ESGN_NON_EXISTENT_PORT" "cout u4 " "Error: Port \"cout\" does not exist in macrofunction \"u4\"" {  } { { "fadder4.vhd" "u4" { Text "F:/eda/fadder4/fadder4.vhd" 19 0 0 } }  } 0 0 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "" 0}
{ "Error" "ESGN_NON_EXISTENT_PORT" "sum u4 " "Error: Port \"sum\" does not exist in macrofunction \"u4\"" {  } { { "fadder4.vhd" "u4" { Text "F:/eda/fadder4/fadder4.vhd" 19 0 0 } }  } 0 0 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "" 0}
{ "Error" "ESGN_NON_EXISTENT_PORT" "cout u3 " "Error: Port \"cout\" does not exist in macrofunction \"u3\"" {  } { { "fadder4.vhd" "u3" { Text "F:/eda/fadder4/fadder4.vhd" 18 0 0 } }  } 0 0 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "" 0}
{ "Error" "ESGN_NON_EXISTENT_PORT" "sum u3 " "Error: Port \"sum\" does not exist in macrofunction \"u3\"" {  } { { "fadder4.vhd" "u3" { Text "F:/eda/fadder4/fadder4.vhd" 18 0 0 } }  } 0 0 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "" 0}
{ "Error" "ESGN_NON_EXISTENT_PORT" "cout u2 " "Error: Port \"cout\" does not exist in macrofunction \"u2\"" {  } { { "fadder4.vhd" "u2" { Text "F:/eda/fadder4/fadder4.vhd" 17 0 0 } }  } 0 0 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "" 0}
{ "Error" "ESGN_NON_EXISTENT_PORT" "sum u2 " "Error: Port \"sum\" does not exist in macrofunction \"u2\"" {  } { { "fadder4.vhd" "u2" { Text "F:/eda/fadder4/fadder4.vhd" 17 0 0 } }  } 0 0 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "" 0}
{ "Error" "ESGN_NON_EXISTENT_PORT" "cout u1 " "Error: Port \"cout\" does not exist in macrofunction \"u1\"" {  } { { "fadder4.vhd" "u1" { Text "F:/eda/fadder4/fadder4.vhd" 16 0 0 } }  } 0 0 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "" 0}
{ "Error" "ESGN_NON_EXISTENT_PORT" "sum u1 " "Error: Port \"sum\" does not exist in macrofunction \"u1\"" {  } { { "fadder4.vhd" "u1" { Text "F:/eda/fadder4/fadder4.vhd" 16 0 0 } }  } 0 0 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 8 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 8 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "152 " "Info: Allocated 152 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Sun Apr 20 20:47:43 2008 " "Error: Processing ended: Sun Apr 20 20:47:43 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 8 s 0 s " "Error: Quartus II Full Compilation was unsuccessful. 8 errors, 0 warnings" {  } {  } 0 0 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}