fadder1.vhd.bak

VHDL实现四位全加器

library ieee;
use ieee.std_logic_1164.all;
entity fadder1 is
port(a,b,cin:in std_logic;
     co,so: out std_logic);
end entity fadder1;
architecture fd of fadder1 is
begin 
  so<=a XOR b XOR ci;
  co<=(a AND b)OR((a XOR b)AND cin);
end architecture fd;